/home/web/htmldatasheet/RUSSIAN/html/cypress/169413

16K x 16/18 Dual-Port Static RAM

CY7C026A
CY7C036A

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-06046 Rev. *A

Revised December 27, 2002

25/0251

Features

· True dual-ported memory cells which allow simulta-

neous access of the same memory location

· 16K x 16 organization (CY7C026A)
· 16K x 18 organization (CY7C036A)
· 0.35-micron CMOS for optimum speed/power
· High-speed access: 12

[1]

/15/20 ns

· Low operating power

-- Active: I

= 180 mA (typical)

-- Standby: I

SB3

= 0.05 mA (typical)

· Fully asynchronous operation

· Automatic power-down
· Expandable data bus to 32/36 bits or more using Mas-

ter/Slave chip select when using more than one device

· On-chip arbitration logic
· Semaphores included to permit software handshaking

between ports

· INT flags for port-to-port communication
· Separate upper-byte and lower-byte control
· Pin select for Master or Slave
· Commercial and Industrial temperature ranges
· Available in 100-Pin TQFP
· Pin-compatible and functionally equivalent to IDT70261

Notes:

See page 6 for Load Conditions.

I/O

for x16 devices; I/O

I/O

for x18 devices.

I/O

for x16 devices; I/O

I/O

for x18 devices.

BUSY is an output in master mode and an input in slave mode.

R/W

I/O

8/9L

I/O

15/17L

I/O

Control

Address

Decode

13L

R/W

BUSY

I/O

Control

Interrupt

Semaphore

Arbitration

SEM

INT

M/S

I/O

7/8L

R/W

I/O

8/9L

I/O

15/17R

I/O

7/8R

Logic Block Diagram

13L

True Dual-Ported

RAM Array

13R

R/W

BUSY

SEM

INT

Address

Decode

13R

[2]

[3]

[4]

8/9

For the most recent information, visit the Cypress web site at www.cypress.com

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 2 of 18

Functional Description

The CY7C026A and CY7C036A are low-power CMOS 16K x
16/18 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple pro-
cessors access the same piece of data. Two ports are provid-
ed, permitting independent, asynchronous access for reads
and writes to any location in memory. The devices can be uti-
lized as standalone 16/18-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 32/36-bit or
wider master/slave dual-port static RAM. An M/S pin is provid-
ed for implementing 32/36-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor designs, communications status buffer-
ing, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by the chip enable pin.

The CY7C026A and CY7C036A are available in 100-pin Thin
Quad Plastic Flatpack (TQFP) packages.

Pin Configurations

100-Pin TQFP (Top View)

92 91 90

87 86

83 82 81

78 77

100

INT

GND

M/S

BUSY

INT

BUSY

CY7C026A (16K x 16)

I/O

10L

I/O

11L

I/O

15L

I/O

13L

I/O

14L

GND

I/O

VCC

I/O

GND

I/O

12L

I/O

VCC

I/O

VCC

R/W

GND

I/O

34 35 36

39 40

43 44 45

48 49

10R

13R

GND

R/W

GND

I/O

14R

12R

I/O

15R

I/O

13R

I/O

12R

I/O

10R

I/O

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 3 of 18

Pin Configurations

(continued)

Selection Guide

CY7C026A
CY7C036A

-12

[1]

CY7C026A
CY7C036A

-15

CY7C026A
CY7C036A

-20

Maximum Access Time (ns)

Typical Operating Current (mA)

195

190

180

Typical Standby Current for I

SB1

(mA) (Both Ports TTL Level)

Typical Standby Current for I

SB3

(mA) (Both Ports CMOS Level)

0.05

Top View

100-Pin TQFP

100 99

95 94

27 28

31 32

36 37 38

63
62

89 88

93 92

INT

BUSY

GND

INT

NC
NC

I/O

11L

I/O

12L

I/O

16L

GND

I/O

M/S

BUSY

I/O

15L

GND

I/O

13L

I/O

14L

I/O

83 82 81 80 79 78 77 76

43 44 45 46 47 48 49 50

I/O

GND

I/O

10L

I/O

16R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

R/W

10R

I/O

17L

I/O

17R

R/W

CY7C036A (16K x 18)

13L

13R

12L

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 4 of 18

Maximum Ratings

[5]

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature .................................65

C to +150

Ambient Temperature with
Power Applied.............................................55

C to +125

Supply Voltage to Ground Potential ............... 0.3V to +7.0V

DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V

DC Input Voltage

[6]

........................................0.5V to + 7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... >2001V

Latch-Up Current .................................................... >200 mA

Note:

The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

Pulse width < 20 ns.

Pin Definitions

Left Port

Right Port

Description

Chip Enable

R/W

Read/Write Enable

Output Enable

13L

13R

Address

I/O

17L

I/O

17R

Data Bus Input/Output

SEM

Semaphore Enable

Upper Byte Select (I/O

I/O

for x16 devices; I/O

I/O

for x18 devices)

Lower Byte Select (I/O

I/O

for x16 devices; I/O

I/O

for x18 devices)

INT

Interrupt Flag

BUSY

Busy Flag

M/S

Master or Slave Select

Power

GND

Ground

No Connect

Operating Range

Range

Ambient

Temperature

Commercial

C to +70

10%

Industrial

C to +85

C 5V

10%

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 5 of 18

Notes:

MAX

= 1/t

= All inputs cycling at f = 1/t

(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level

standby I

SB3

Tested initially and after any design or process changes that may affect these parameters.

Electrical Characteristics

Over the Operating Range

Parameter

Description

CY7C026A
CY7C036A

Unit

-12

[1]

-15

-20

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Output HIGH Voltage (V

=Min., I

4.0 mA)

2.4

Output LOW Voltage (V

=Min., I

+4.0 mA)

0.4

Input HIGH Voltage

2.2

Input LOW Voltage

0.8

Output Leakage Current

Operating Current (V

= Max.,

OUT

= 0 mA) Outputs Disabled

Com'l.

195

325

190

285

180

275

Indust.

215

305

SB1

Standby Current
(Both Ports TTL Level)
CE

& CE

, f = f

MAX

Com'l.

Indust.

SB2

Standby Current
(One Port TTL Level)
CE

| CE

, f = f

MAX

Com'l.

125

205

120

180

110

160

Indust.

135

205

SB3

Standby Current
(Both Ports CMOS Level)
CE

& CE

0.2V, f = 0

Com'l.

0.05

0.5

0.05

0.5

0.05

0.5

Indust.

0.05

0.5

SB4

Standby Current
(One Port CMOS Level)
CE

| CE

, f = f

MAX

[7]

Com'l.

115

185

110

160

100

140

Indust.

125

175

Capacitance

[8]

Parameter

Description

Test Conditions

Max.

Unit

Input Capacitance

= 25

C, f = 1 MHz,

= 5.0V

OUT

Output Capacitance

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 7 of 18

Switching Characteristics

Over the Operating Range

[10]

Parameter

Description

CY7C026A
CY7C036A

Unit

-12

[1]

-15

-20

Min.

Max.

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

Address to Data Valid

OHA

Output Hold From Address Change

ACE

[11]

CE LOW to Data Valid

DOE

OE LOW to Data Valid

LZOE

[12, 13, 14]

OE LOW to Low Z

HZOE

[12, 13, 14]

OE HIGH to High Z

LZCE

[12, 13, 14]

CE LOW to Low Z

HZCE

[12, 13, 14]

CE HIGH to High Z

[14]

CE LOW to Power-Up

[14]

CE HIGH to Power-Down

ABE

[11]

Byte Enable Access Time

WRITE CYCLE

Write Cycle Time

SCE

[11]

CE LOW to Write End

Address Valid to Write End

Address Hold From Write End

[11]

Address Set-Up to Write Start

PWE

Write Pulse Width

Data Set-Up to Write End

[16]

Data Hold From Write End

HZWE

[13, 14]

R/W LOW to High Z

LZWE

[13, 14]

R/W HIGH to Low Z

WDD

[15]

Write Pulse to Data Delay

DDD

[15]

Write Data Valid to Read Data Valid

Notes:

10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

and 30-pF load capacitance.

11.

To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t

SCE

time.

12. At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

13. Test conditions used are Load 3.
14. This parameter is guaranteed but not tested.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. For 15 ns industrial parts t

Min. is 0.5 ns.

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 8 of 18

Data Retention Mode

The CY7C026A and CY7C036A are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:

1. Chip Enable (CE) must be held HIGH during data retention, with-

in V

to V

0.2V.

2. CE must be kept between V

0.2V and 70% of V

during the power-up and power-down transitions.

3. The RAM can begin operation >t

after V

reaches the

minimum operating voltage (4.5 volts).

Notes:

17. Test conditions used are Load 2.
18. t

BDD

is a calculated parameter and is the greater of t

WDD

PWE

(actual) or t

DDD

(actual).

19. CE = V

, V

= GND to V

, T

= 25

C. This parameter is guaranteed but not tested.

BUSY TIMING

[17]

BLA

BUSY LOW from Address Match

BHA

BUSY HIGH from Address Mismatch

BLC

BUSY LOW from CE LOW

BHC

BUSY HIGH from CE HIGH

Port Set-Up for Priority

R/W HIGH after BUSY (Slave)

R/W HIGH after BUSY HIGH (Slave)

BDD

[18]

BUSY HIGH to Data Valid

INTERRUPT TIMING

[17]

INS

INT Set Time

INR

INT Reset Time

SEMAPHORE TIMING

SOP

SEM Flag Update Pulse (OE or SEM)

SWRD

SEM Flag Write to Read Time

SPS

SEM Flag Contention Window

SAA

SEM Address Access Time

Switching Characteristics

Over the Operating Range

[10]

(continued)

Parameter

Description

CY7C026A
CY7C036A

Unit

-12

[1]

-15

-20

Min.

Max.

Min.

Max.

Min.

Max.

Timing

Parameter

Test Conditions

[19]

Max.

Unit

ICC

DR1

@ VCC

= 2V

1.5

Data Retention Mode

4.5V

2.0V

to V

0.2V

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 10 of 18

Notes:

25. R/W must be HIGH during all address transitions.
26. A write occurs during the overlap (t

SCE

or t

PWE

) of a LOW CE or SEM and a LOW UB or LB.

27. t

is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

28. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or (t

HZWE

+ t

) to allow the I/O drivers to turn off and

data to be placed on the bus for the required t

. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse

can be as short as the specified t

PWE

29. To access RAM, CE = V

, SEM = V

30. To access upper byte, CE = V

, UB = V

, SEM = V

To access lower byte, CE = V

, LB = V

, SEM = V

31. Transition is measured

500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

32. During this period, the I/O pins are in the output state, and input signals must not be applied.
33. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

Switching Waveforms

(continued)

PWE

R/W

DATA OUT

DATA IN

ADDRESS

HZOE

HZWE

LZWE

Write Cycle No. 1: R/W Controlled Timing

[25, 26, 27, 28]

[31]

[28]

[29,30]

NOTE 32

SCE

R/W

DATA IN

ADDRESS

Write Cycle No. 2: CE Controlled Timing

[25, 26, 27, 33]

[29,30]

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 15 of 18

Architecture

The CY7C026A and CY7C036A consist of an array of 16K
words of 16 and 18 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE, OE, R/W). These con-
trol pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to
the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be utilized for port-to-port communica-
tion. Two Semaphore (SEM) control pins are used for allocat-
ing shared resources. With the M/S pin, the devices can func-
tion as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The devices also have an automatic power-
down feature controlled by CE. Each port is provided with its
own Output Enable control (OE), which allows data to be read
from the device.

Functional Description

Write Operation

Data must be set up for a duration of t

before the rising edge

of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1 wave-
form) or the CE pin (see Write Cycle No. 2 waveform). Re-
quired inputs for non-contention operations are summarized in
Table 1.

If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port t

DDD

after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE
and CE pins. Data will be available t

ACE

after CE or t

DOE

after

OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.

Interrupts

The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox
for the right port and the second-highest memory location
(3FFE) is the mailbox for the left port. When one port writes to
the other port's mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.

Each port can read the other port's mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not
connect the interrupt pin to the processor's interrupt request
input pin.

The operation of the interrupts and their interaction with Busy
are summarized in Table 2.

Busy

The CY7C026A and CY7C036A provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports' CEs are asserted and an address match occurs

within t

of each other, the busy logic will determine which

port has access. If t

is violated, one port will definitely gain

permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted t

BLA

after an

address match or t

BLC

after CE is taken LOW.

Master/Slave

A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (t

BLC

or t

BLA

otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.

Semaphore Operation

The CY7C026A and CY7C036A provide eight semaphore
latches, which are separate from the dual-port memory loca-
tions. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for t

SOP

before

attempting to read the semaphore. The semaphore value will
be available t

SWRD

+ t

DOE

after the rising edge of the sema-

phore write. If the left port was successful (reads a zero), it
assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll
the semaphore. When the right side has relinquished control
of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A

represents the

semaphore address. OE and R/W are used in the same man-
ner as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O

is used. If a zero is

written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes con-
trol by writing a one to the semaphore, the semaphore will be
set to one for both sides. However, if the right port had request-
ed the semaphore (written a zero) while the left port had con-
trol, the right port would immediately own the semaphore as
soon as the left port released it. Table 3 shows sample sema-
phore operations.

When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to ac-
cess the semaphore within t

SPS

of each other, the semaphore

will definitely be obtained by one side or the other, but there is
no guarantee which side will control the semaphore.

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 16 of 18

Table 1. Non-Contending Read/Write

Inputs

Outputs

R/W

SEM

I/O

Operation

High Z

Deselected: Power-Down

High Z

Deselected: Power-Down

Data In

High Z

Write to Upper Byte Only

High Z

Data In

Write to Lower Byte Only

Data In

Write to Both Bytes

Data Out

High Z

Read Upper Byte Only

High Z

Data Out

Read Lower Byte Only

Data Out

Read Both Bytes

High Z

Outputs Disabled

Data Out

Read Data in Semaphore Flag

Data Out

Read Data in Semaphore Flag

Data In

Write D

IN0

into Semaphore Flag

Data In

Write D

IN0

into Semaphore Flag

Not Allowed

Table 2. Interrupt Operation Example (assumes BUSY

=BUSY

=HIGH)

Left Port

Right Port

Function

R/W

0L13L

INT

R/W

0R13R

INT

Set Right INT

Flag

3FFF

[43]

Reset Right INT

Flag

3FFF

[42]

Set Left INT

Flag

[42]

3FFE

Reset Left INT

Flag

3FFE

[43]

Table 3. Semaphore Operation Example

Function

I/O

Left

I/O

Right

Status

No action

Semaphore free

Left port writes 0 to semaphore

Left Port has semaphore token

Right port writes 0 to semaphore

No change. Right side has no write access to semaphore

Left port writes 1 to semaphore

Right port obtains semaphore token

Left port writes 0 to semaphore

No change. Left port has no write access to semaphore

Right port writes 1 to semaphore

Left port obtains semaphore token

Left port writes 1 to semaphore

Semaphore free

Right port writes 0 to semaphore

Right port has semaphore token

Right port writes 1 to semaphore

Semaphore free

Left port writes 0 to semaphore

Left port has semaphore token

Left port writes 1 to semaphore

Semaphore free

Notes:

42. If BUSY

=L, then no change.

43. If BUSY

=L, then no change.

CY7C026A

CY7C036A

Document #: 38-06046 Rev. *A

Page 17 of 18

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Ordering Information

16K x16 Asynchronous Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

[1]

CY7C026A-12AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C026A-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C026A-15AI

A100

100-Pin Thin Quad Flat Pack

Industrial

CY7C026A-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

16K x18 Asynchronous Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

[1]

CY7C036A-12AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C036A-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

CY7C036A-15AI

A100

100-Pin Thin Quad Flat Pack

Industrial

CY7C036A-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

Package Diagram

100-Pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-B

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY7C026A-20AC

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY7C026A-20AC