128K x 8 Static RAM
CY7C1019CV33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05130 Rev. *D
Revised December 16, 2002
Features
Pin and function compatible with CY7C1019BV33
High speed
-- t
AA
= 8, 10, 12, 15 ns
CMOS for optimum speed/power
Data retention at 2.0V
Center power/ground pinout
Automatic power-down when deselected
Easy memory expansion with CE
and OE options
Available in 32-pin TSOP II and 400-mil SOJ package
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019CV33 is available in a standard 32-pin TSOP
II and 400-mil-wide SOJ.
14
15
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DE
CODE
R
SE
N
S
E AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ/TSOP II
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
Selection Guide
7C1019CV33-8
7C1019CV33-10
7C1019CV33-12
7C1019CV33-15
Unit
Maximum Access Time
8
10
12
15
ns
Maximum Operating Current
85
80
75
70
mA
Maximum Standby Current
5
5
5
5
mA
CY7C1019CV33
Document #: 38-05130 Rev. *D
Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied............................................. 55C to +125C
Supply Voltage on V
CC
to Relative GND
[1]
... 0.5V to + 4.6V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0C to +70C
3.3V
10%
Industrial
40
C to +85
C
3.3V
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
7C1019CV33
-8
7C1019CV33
-10
7C1019CV33
-12
7C1019CV33
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3
2.0
V
CC
+ 0.3
2.0
V
CC
+ 0.3
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
I
< V
CC
,
Output Disabled
1
+1
1
+1
1
+1
1
+1
A
I
OS
[2.]
Output Short
Circuit Current
V
CC
= Max.,
V
OUT
= GND
300
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
85
80
75
70
mA
I
SB1
Automatic CE
Power-down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
15
15
15
15
mA
I
SB2
Automatic CE
Power-down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
5
5
5
5
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= 5.0V
8
pF
C
OUT
Output Capacitance
8
pF
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3.
Tested initially and after any design or process changes that may affect these parameters.
CY7C1019CV33
Document #: 38-05130 Rev. *D
Page 3 of 8
AC Test Loads and Waveforms
[4]
Switching Characteristics
[5]
Over the Operating Range
Parameter
Description
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
8
10
12
15
ns
t
AA
Address to Data Valid
8
10
12
15
ns
t
OHA
Data Hold from Address Change
3
3
3
3
ns
t
ACE
CE LOW to Data Valid
8
10
12
15
ns
t
DOE
OE LOW to Data Valid
5
5
6
7
ns
t
LZOE
OE LOW to Low Z
0
0
0
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
4
5
6
7
ns
t
LZCE
CE LOW to Low Z
[7]
3
3
3
3
ns
t
HZCE
CE HIGH to High Z
[6, 7]
4
5
6
7
ns
t
PU
[8]
CE LOW to Power-Up
0
0
0
0
ns
t
PD
[8]
CE HIGH to Power-Down
8
10
12
15
ns
Write Cycle
[9, 10]
t
WC
Write Cycle Time
8
10
12
15
ns
t
SCE
CE LOW to Write End
7
8
9
10
ns
t
AW
Address Set-Up to Write End
7
8
9
10
ns
t
HA
Address Hold from Write End
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
ns
t
PWE
WE Pulse Width
6
7
8
10
ns
t
SD
Data Set-Up to Write End
5
5
6
8
ns
t
HD
Data Hold from Write End
0
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
3
3
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
4
5
6
7
ns
Notes:
4.
AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
This parameter is guaranteed by design and is not tested.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30pF*
OUTPUT
Z = 50
50
1.5V
(c)
(a)
3.3V
OUTPUT
5 pF
(d)
R 317
R2
351
8-ns devices:
10-, 12-, 15-ns devices:
High-Z characteristics:
CY7C1019CV33
Document #: 38-05130 Rev. *D
Page 4 of 8
Switching Waveforms
Read Cycle No. 1
[11, 12]
Read Cycle No. 2 (OE Controlled)
[12, 13]
Write Cycle No. 1 (CE Controlled)
[14, 15]
Notes:
11. Device is continuously selected. OE, CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
IH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
CY7C1019CV33
Document #: 38-05130 Rev. *D
Page 5 of 8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[14, 15]
Write Cycle No. 3 (WE Controlled, OE LOW)
[15]
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE
16
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
16
Truth Table
CE
OE
WE
I/O
0
I/O
7
Mode
Power
H
X
X
High Z
Power-Down
Standby (I
SB
)
L
L
H
Data Out
Read
Active (I
CC
)
L
X
L
Data In
Write
Active (I
CC
)
L
H
H
High Z
Selected, Outputs Disabled
Active (I
CC
)
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
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