PRELIMINARY
128K x 8 Static RAM
CY7C1019
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05055 Rev. **
Revised August 31, 2001
019
Features
High speed
-- t
AA
= 10 ns
CMOS for optimum speed/power
Center power/ground pinout
Automatic power-down when deselected
Easy memory expansion with CE
and OE options
Functional Description
The CY7C1019 is a high-performance CMOS static RAM or-
ganized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location speci-
fied on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write
enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019 is available in standard 400-mil-wide SOJs.
14
15
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DEC
O
D
E
R
SE
NSE A
M
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
10191
10192
V
SS
Selection Guide
7C101910
7C101912
7C101915
Maximum Access Time (ns)
10
12
15
Maximum Operating Current (mA)
240
220
200
L
210
190
175
Maximum Standby Current (mA)
10
10
10
L
1
1
1
Shaded areas contain advance information.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Electrical Characteristics
Over the Operating Range
Test Conditions
7C1019-10
7C1019-12
7C1019-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
I
< V
CC
,
Output Disabled
5
+5
5
+5
5
+5
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
240
220
200
mA
L
210
190
175
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
40
40
40
mA
L
20
20
20
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f=0
10
10
10
mA
L
1
1
1
Shaded areas contain advance information.
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
6
pF
C
OUT
Output Capacitance
8
pF
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "instant on" case temperature.
3.
Tested initially and after any design or process changes that may affect these parameters.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
10193
10194
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
3ns
3 ns
OUTPUT
R1 480
R1 480
R2
255
R2
255
167
Equivalent to:
VENIN EQUIVALENT
1.73V
TH
Switching Characteristics
[4]
Over the Operating Range
7C1019-10
7C1019-12
7C1019-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
12
15
ns
t
AA
Address to Data Valid
10
12
15
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE LOW to Data Valid
10
12
15
ns
t
DOE
OE LOW to Data Valid
5
6
7
ns
t
LZOE
OE LOW to Low Z
0
0
0
ns
t
HZOE
OE HIGH to High Z
[5, 6]
5
6
7
ns
t
LZCE
CE LOW to Low Z
[6]
3
3
3
ns
t
HZCE
CE HIGH to High Z
[5, 6]
5
6
7
ns
t
PU
CE LOW to Power-Up
0
0
0
ns
t
PD
CE HIGH to Power-Down
10
12
15
ns
WRITE CYCLE
[7,8]
t
WC
Write Cycle Time
10
12
15
ns
t
SCE
CE LOW to Write End
8
9
10
ns
t
AW
Address Set-Up to Write End
7
8
10
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
7
8
10
ns
t
SD
Data Set-Up to Write End
5
6
8
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[6]
3
3
3
ns
t
HZWE
WE LOW to High Z
[5, 6]
5
6
7
ns
Shaded areas contain advance information.
Note:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
6.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 4 of 8
Data Retention Characteristics
Over the Operating Range (L Version Only)
Parameter
Description
Conditions
Min.
Max
Unit
V
DR
V
CC
for Data Retention
No input may exceed V
CC
+ 0.5V
V
CC
= V
DR
= 3.0V,
CE
1
> V
CC
0.3V,
V
IN
> V
CC
0.3V or V
IN
< 0.3V
2.0
V
I
CCDR
Data Retention Current
300
A
t
CDR
[3]
Chip Deselect to Data Retention Time
0
ns
t
R
Operation Recovery Time
t
RC
ns
Data Retention Waveform
10195
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Waveforms
Read Cycle No. 1
[9, 10]
Read Cycle No. 2 (OE Controlled)
[10, 11]
Notes:
9.
Device is continuously selected. OE, CE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
10196
ADDRESS
DATA OUT
10197
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 5 of 8
Write Cycle No. 1 (CE Controlled)
[12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[12, 13]
Notes:
12. Data I/O is high impedance if OE = V
IH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
10198
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
10199
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE
14
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 6 of 8
Write Cycle No. 3 (WE Controlled, OE LOW)
[13]
Switching Waveforms
(continued)
101910
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
14
Truth Table
CE
OE
WE
I/O
0
I/O
7
Mode
Power
H
X
X
High Z
Power-Down
Standby (I
SB
)
X
X
X
High Z
Power-Down
Standby (I
SB
)
L
L
H
Data Out
Read
Active (I
CC
)
L
X
L
Data In
Write
Active (I
CC
)
L
H
H
High Z
Selected, Outputs Disabled
Active (I
CC
)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
10
CY7C1019-10VC
V33
32-Lead 400-Mil Molded SOJ
Commercial
CY7C1019L-10VC
V33
32-Lead 400-Mil Molded SOJ
12
CY7C1019-12VC
V33
32-Lead 400-Mil Molded SOJ
Commercial
CY7C1019L-12VC
V33
32-Lead 400-Mil Molded SOJ
15
CY7C1019-15VC
V33
32-Lead 400-Mil Molded SOJ
Commercial
CY7C1019L-15VC
V33
32-Lead 400-Mil Molded SOJ
Shaded area contains advance information.
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 7 of 8
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
32-Lead (400-Mil) Molded SOJ V33
CY7C1019
PRELIMINARY
Document #: 38-05055 Rev. **
Page 8 of 8
Document Title: 7C1019 128K x 8 Static RAM
Document Number: 38-05055
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107246
09/10/01
SZV
Change from Spec number: 38-00440 to 38-05055
PDF 
ZIP