32K x 16 Static RAM
CY7C1020CV33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05133 Rev. *B
Revised August 13, 2002
Features
Pin- and function-compatible with CY7C1020V33
High speed
-- t
AA
= 10, 12, 15 ns
CMOS for optimum speed/power
Low active power
-- 360 mW (max.)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II
Functional Description
The CY7C1020CV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
14
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
14
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020CV33 is available in standard 44-pin TSOP
Type II packages.
Selection Guide
1020CV33-10
1020CV33-12
1020CV33-15
Unit
Maximum Access Time
10
12
15
ns
Maximum Operating Current
90
85
80
mA
Maximum CMOS Standby Current
5
5
5
mA
WE
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15
29
30
V
CC
A
14
A
13
A
12
NC
NC
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
NC
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
NC
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
32K 16
RAM Array
I/O
1
I/O
8
ROW
DE
CODE
R
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
S
E
N
S
E AM
PS
DATA IN DRIVERS
OE
A
2
A
1
I/O
9
I/O
16
CE
WE
BLE
BHE
A
8
A
4
CY7C1020CV33
Document #: 38-05133 Rev. *B
Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................ 0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
V
CC
Commercial
0
C to +70
C 3.3V
10%
Industrial
40
C to +85
C
3.3V
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
1020CV33-10
1020CV33-12
1020CV33-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
V
OH
Output HIGH Voltage V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+
0.3
2.0
V
CC
+
0.3
2.0
V
CC
+
0.3
V
V
IL
Input LOW Voltage
[1]
-
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
1
+1
1
+1
1
+1
A
I
OZ
Output
Leakage Current
GND < V
I
< V
CC
,
Output Disabled
-
1
+1
1
+1
1
+1
A
I
OS
[2]
Output Short
Circuit Current
V
CC
= Max.,
V
OUT
= GND
-
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
90
85
80
mA
I
SB1
Automatic CE
Power-down Current
--TTL Inputs
Max. V
CC
,
CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
,
f = f
MAX
15
15
15
mA
I
SB2
Automatic CE
Power-down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V, V
IN
>
V
CC
0.3V,
or V
IN
< 0.3V, f = 0
5
5
5
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 3.3V
8
pF
C
OUT
Output Capacitance
8
pF
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3.
Tested initially and after any design or process changes that may affect these parameters.
CY7C1020CV33
Document #: 38-05133 Rev. *B
Page 3 of 8
AC Test Loads and Waveforms
[4]
Switching Characteristics
Over the Operating Range
[4]
Parameter
Description
1020CV33-10
1020CV33-12
1020CV33-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
10
12
15
ns
t
AA
Address to Data Valid
10
12
15
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE LOW to Data Valid
10
12
15
ns
t
DOE
OE LOW to Data Valid
5
6
7
ns
t
LZOE
OE LOW to Low-Z
[5]
0
0
0
ns
t
HZOE
OE HIGH to High-Z
[5, 6]
5
6
7
ns
t
LZCE
CE LOW to Low-Z
[5]
3
3
3
ns
t
HZCE
CE HIGH to High-Z
[5, 6]
5
6
7
ns
t
PU
[7]
CE LOW to Power-up
0
0
0
ns
t
PD
[7]
CE HIGH to Power-down
10
12
15
ns
t
DBE
Byte Enable to Data Valid
5
6
7
ns
t
LZBE
Byte Enable to Low-Z
0
0
0
ns
t
HZBE
Byte Disable to High-Z
5
6
7
ns
Write Cycle
[8]
t
WC
Write Cycle Time
10
12
15
ns
t
SCE
CE LOW to Write End
8
9
10
ns
t
AW
Address Set-up to Write End
7
8
10
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
7
8
10
ns
t
SD
Data Set-up to Write End
5
6
8
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low-Z
[5]
3
3
3
ns
t
HZWE
WE LOW to High-Z
[5, 6]
5
6
7
ns
t
BW
Byte Enable to End of Write
7
8
9
ns
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6.
t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
This parameter is guaranteed by design and is not tested.
8.
The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317
R2
351
High-Z characteristics:
CY7C1020CV33
Document #: 38-05133 Rev. *B
Page 4 of 8
Switching Waveforms
Notes:
9.
Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
10. WE is HIGH for Read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Read Cycle No. 1
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
[9, 10]
Read Cycle No. 2 (OE Controlled)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
t
DBE
t
LZBE
t
HZCE
BHE, BLE
[10, 11]
CURRENT
I
CC
I
SB
CY7C1020CV33
Document #: 38-05133 Rev. *B
Page 5 of 8
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE = V
IH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
t
HD
t
SD
t
SCE
t
SA
t
HA
t
AW
t
PWE
t
WC
BW
DATA I/O
ADDRESS
CE
WE
BHE, BLE
[12, 13]
t
Write Cycle No. 2 (BLE or BHE Controlled)
t
HD
t
SD
t
BW
t
SA
t
HA
t
AW
t
PWE
t
WC
t
SCE
DATA I/O
ADDRESS
BHE, BLE
WE
CE
PDF 
ZIP