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256K x 4 Static RAM
CY7C106B
CY7C1006B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05037 Rev. **
Revised August 24, 2001
1CY7C1006B
Features
High speed
-- t
AA
=
12 ns
CMOS for optimum speed/power
Low active power
-- 495 mW
Low standby power
-- 275 mW
2.0V data retention (optional)
-- 100
W
Automatic power-down when deselected
TTL-compatible inputs and outputs
Functional Description
The CY7C106B and CY7C1006B are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic pow-
er-down feature that reduces power consumption by more
than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
0
through I/O
3
) is then written into the location speci-
fied on the address pins (A
0
through A
17
).
Reading from the devices is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106B is available in a standard 400-mil-wide SOJ;
the CY7C1006B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
C106B1
C106B2
512 x 512 x 4
ARRAY
A
1
A
0
A
10
A
12
A
11
A
13
A
14
COLUMN
DECODER
R
O
W
DE
CODE
R
S
E
N
S
E AM
PS
POWER
DOWN
OE
INPUT BUFFER
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
V
CC
A
16
A
15
A
14
A
13
I/O
3
I/O
2
I/O
1
I/O
0
A
9
A
0
A
10
CE
OE
NC
A
12
A
11
WE
WE
CE
I/O
0
I/O
1
I/O
2
I/O
3
A
2
A
3
A
4
A
6
A
7
A
8
A
9
A
5
Selection Guide
7C106B-12
7C1006B-12
7C106B-15
7C1006B-15
7C106B-20
7C1006B-20
7C106B-25
7C1006B-25
7C106B-35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating
Current (mA)
90
80
75
70
60
Maximum Standby
Current (mA)
50
30
30
30
25
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. **
Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied ............................................. 55
C to +125
C
Supply Voltage on V
CC
Relative to GND
[1]
.... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Industrial
45
C to +85
C
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. **
Page 3 of 10
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
7C106B-12
7C1006B-12
7C106B-15
7C1006B-15
7C106B-20
7C1006B-20
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+0.3
2.2
V
CC
+0.3
2.2
V
CC
+0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage Current
GND < V
I
< V
CC
,
Output Disabled
5
+5
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
90
80
75
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
50
30
30
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V
or V
IN
< 0.3V, f=0
Com'l
10
10
10
mA
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+
0.3
2.2
V
CC
+
0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
A
I
OZ
Output Leakage Current
GND < V
I
< V
CC
,
Output Disabled
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
70
60
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
30
25
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V
or V
IN
< 0.3V, f = 0
Com'l
10
10
mA
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "instant on" case temperature.
3.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. **
Page 4 of 10
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
: Addresses
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
7
pF
C
IN
: Controls
10
pF
C
OUT
Output Capacitance
10
pF
AC Test Loads and Waveforms
Note:
4.
Tested initially and after any design or process changes that may affect these parameters.
C106B3
C106B4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R1 480
R1 480
R2
255
R2
255
167
Equivalent to:
TH VENIN EQUIVALENT
1.73V
Rise Time < 1V/ns
Fall Time < 1V/ns
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. **
Page 5 of 10
Switching Characteristics
Over the Operating Range
[5]
7C106B-12
7C1006B-12
7C106B-15
7C1006B-15
7C106B-20
7C1006B-20
7C106B-25
7C1006B-25
7C106B-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
t
RC
Read Cycle Time
12
15
20
25
35
ns
t
AA
Address to Data Valid
12
15
20
25
35
ns
t
OHA
Data Hold from Address Change
3
3
3
3
3
ns
t
ACE
CE LOW to Data Valid
12
15
20
25
35
ns
t
DOE
OE LOW to Data Valid
6
7
8
10
10
ns
t
LZOE
OE LOW to Low Z
0
0
0
0
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
6
7
8
10
10
ns
t
LZCE
CE LOW to Low Z
[7]
3
3
3
3
3
ns
t
HZCE
CE HIGH to High Z
[6, 7]
6
7
8
10
10
ns
t
PU
CE LOW to Power-Up
0
0
0
0
0
ns
t
PD
CE HIGH to Power-Down
12
15
20
25
35
ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time
12
15
20
25
35
ns
t
SCE
CE LOW to Write End
10
12
15
20
25
ns
t
AW
Address Set-Up to Write End
10
12
15
20
25
ns
t
HA
Address Hold from Write End
0
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
0
ns
t
PWE
WE Pulse Width
10
12
15
20
25
ns
t
SD
Data Set-Up to Write End
7
8
10
15
20
ns
t
HD
Data Hold from Write End
0
0
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
2
3
3
3
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
6
7
8
10
10
ns
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30pF load capacitance.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
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