128K x 8 Static RAM
CY7C109B
CY7C1009B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05038 Rev. **
Revised August 24, 2001
009B
Features
High speed
-- t
AA
= 12 ns
Low active power
-- 495 mW (max. 12 ns)
Low CMOS standby power
-- 55 mW (max.) 4 mW
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy mem-
ory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE
2
) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109B is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009B is available in
a 300-mil-wide SOJ package. The CY7C1009B and
CY7C109B are functionally equivalent in all other respects.
14
15
Logic Block Diagram
Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODE
R
SENS
E AM
PS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
1
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
109B1
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
109B2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
109B3
Selection Guide
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating Current (mA)
90
80
75
70
60
Maximum CMOS Standby Current (mA)
10
10
10
10
10
Maximum CMOS Standby Current (mA)
Low Power Version
2
2
2
-
-
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 2 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Industrial
-
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range
Test Conditions
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
Parameter
Description
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
I
< V
CC
,
Output Disabled
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max.,
V
OUT
= GND
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
90
80
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
45
40
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE
1
> V
CC
0.3V,
or CE
2
< 0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
10
10
mA
L
2
2
mA
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the case temperature.
3.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 3 of 12
Electrical Characteristics
Over the Operating Range (continued)
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage
Current
GND < V
I
< V
CC
,
Output Disabled
5
+5
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max.,
V
OUT
= GND
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
75
70
60
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
Max. V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
30
30
25
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
Max. V
CC
,
CE
1
> V
CC
0.3V,
or CE
2
< 0.3V,
V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f = 0
10
10
10
mA
L
2
--
--
mA
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
9
pF
C
OUT
Output Capacitance
8
pF
AC Test Loads and Waveforms
Note:
4.
Tested initially and after any design or process changes that may affect these parameters.
10B94
109B5
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
3 ns
3 ns
OUTPUT
R1 480
R1 480
R2
255
R2
255
167
Equivalent to:
VENIN EQUIVALENT
1.73V
TH
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 4 of 12
Switching Characteristics
[5]
Over the Operating Range
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
12
15
ns
t
AA
Address to Data Valid
12
15
ns
t
OHA
Data Hold from Address Change
3
3
ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data
Valid
12
15
ns
t
DOE
OE LOW to Data Valid
6
7
ns
t
LZOE
OE LOW to Low Z
0
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
6
7
ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[7]
3
3
ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[6, 7]
6
7
ns
t
PU
CE
1
LOW to Power-Up, CE
2
HIGH to
Power-Up
0
0
ns
t
PD
CE
1
HIGH to Power-Down, CE
2
LOW to
Power-Down
12
15
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
[9]
12
15
ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End
10
12
ns
t
AW
Address Set-Up to Write End
10
12
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
10
12
ns
t
SD
Data Set-Up to Write End
7
8
ns
t
HD
Data Hold from Write End
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
6
7
ns
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 5 of 12
Switching Characteristics
[5]
Over the Operating Range (continued)
Parameter
Description
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Unit
Min.
Max.
Min.
Max.
Min.
Min.
READ CYCLE
t
RC
Read Cycle Time
20
25
35
ns
t
AA
Address to Data Valid
20
25
35
ns
t
OHA
Data Hold from Address Change
3
5
5
ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data
Valid
20
25
35
ns
t
DOE
OE LOW to Data Valid
8
10
15
ns
t
LZOE
OE LOW to Low Z
0
0
0
ns
t
HZOE
OE HIGH to High Z
[6, 7]
8
10
15
ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[7]
3
5
5
ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[6, 7]
8
10
15
ns
t
PU
CE
1
LOW to Power-Up, CE
2
HIGH to
Power-Up
0
0
0
ns
t
PD
CE
1
HIGH to Power-Down, CE
2
LOW to
Power-Down
20
25
35
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
[9]
20
25
35
ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End
15
20
25
ns
t
AW
Address Set-Up to Write End
15
20
25
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
12
15
20
ns
t
SD
Data Set-Up to Write End
10
15
20
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
5
5
ns
t
HZWE
WE LOW to High Z
[6, 7]
8
10
15
ns
Data Retention Characteristics
Over the Operating Range (Low Power version only)
Parameter
Description
Conditions
Min.
Max
Unit
V
DR
V
CC
for Data Retention
No input may exceed V
CC
+ 0.5V
V
CC
= V
DR
= 2.0V,
CE
1
> V
CC
0.3V or CE
2
< 0.3V,
V
IN
> V
CC
0.3V or V
IN
< 0.3V
2.0
V
I
CCDR
Data Retention Current
150
A
t
CDR
Chip Deselect to Data Retention Time
0
ns
t
R
Operation Recovery Time
200
s
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 6 of 12
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
[10, 11]
Read Cycle No. 2 (OE Controlled)
[11, 12]
Notes:
10. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
4.5V
4.5V
CE
V
CC
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
109B-6
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
109B7
ADDRESS
DATA OUT
109B8
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 7 of 12
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[13, 14]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[13, 14]
Notes:
13. Data I/O is high impedance if OE = V
IH
.
14. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
109B9
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O
109B10
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
NOTE
15
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 8 of 12
Write Cycle No. 3 (WE Controlled, OE LOW)
[14]
Switching Waveforms
(continued)
10B911
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
SCE
t
WC
t
HZWE
CE
1
ADDRESS
CE
2
WE
DATA I/O
NOTE
15
Truth Table
CE
1
CE
2
OE
WE
I/O
0
I/O
7
Mode
Power
H
X
X
X
High Z
Power-Down
Standby (I
SB
)
X
L
X
X
High Z
Power-Down
Standby (I
SB
)
L
H
L
H
Data Out
Read
Active (I
CC
)
L
H
X
L
Data In
Write
Active (I
CC
)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (I
CC
)
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 9 of 12
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
12
CY7C109B-12VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C1009B-12VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-12ZC
Z32
32-Lead TSOP Type I
15
CY7C109B-15VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C109BL-15VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-15VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-15ZC
Z32
32-Lead TSOP Type I
CY7C109BL-15ZC
Z32
32-Lead TSOP Type I
CY7C109B-15VI
V33
32-Lead (400-Mil) Molded SOJ
Industrial
CY7C109BL-15VI
V33
32-Lead (400-Mil) Molded SOJ
CY7C1009B-15VI
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-15ZI
Z32
32-Lead TSOP Type I
20
CY7C109B-20VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C1009B-20VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-20VI
V33
32-Lead (400-Mil) Molded SOJ
Industrial
CY7C109B-20ZC
Z32
32-Lead TSOP Type I
Commercial
CY7C109B-20ZI
Z32
32-Lead TSOP Type I
Industrial
25
CY7C109B-25VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C1009B-25VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-25VI
V33
32-Lead (400-Mil) Molded SOJ
Industrial
CY7C109B-25ZC
Z32
32-Lead TSOP Type I
Commercial
CY7C109B-25ZI
Z32
32-Lead TSOP Type I
Industrial
35
CY7C109B-35VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C1009B-35VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C109B-35VI
V33
32-Lead (400-Mil) Molded SOJ
Industrial
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 10 of 12
Package Diagrams
32-Lead (300-Mil) Molded SOJ V32
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 11 of 12
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
51-85056-C
32-Lead Thin Small Outline Package Z32
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. **
Page 12 of 12
Document Title: CY7C109B, CY7C1009 128K x 8 SRAM
Document Number: 38-05038
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106832
09/22/01
SZV
Change from Spec number: 38-00971 to 38-05038
PDF 
ZIP