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1-Mb (32K x 32) Flow-Through Sync SRAM

CY7C1214F

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05434 Rev. *A

Revised March 24, 2004

Features

· 32K X 32 common I/O
· 3.3V 5% and +10% core power supply (V

)

· 3.3V I/O supply (V

DDQ

)

· Fast clock-to-output times

-- 7.5 ns (117-MHz version)
-- 8.5 ns (100-MHz version)

· Provide high-performance 2-1-1-1 access rate
· User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

· Separate processor and controller address strobes
· Synchronous self-timed write
· Asynchronous output enable
· Supports 3.3V I/O level
· Offered in JEDEC-standard 100-pin TQFP package
· "ZZ" Sleep Mode option

Functional Description

[1]

The CY7C1214F is a 32,768 x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

7.5 ns (117-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1214F allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).
The CY7C1214F operates from a +3.3V core power supply

while all outputs may operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

Logic Block Diagram

ADDRESS
REGISTER

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

[1:0]

DQs

A0, A1, A

ADV

CLK

ADSP

ADSC

BWE

CE1

CE2

CE3

SLEEP

CONTROL

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

CY7C1214F

Document #: 38-05434 Rev. *A

Page 2 of 15

Selection Guide

117 MHz

100 MHz

Unit

Maximum Access Time

7.5

8.0

Maximum Operating Current

220

205

Maximum Standby Current

Shaded area contain advance information. Please contact your local Cypress sales representative for availability of this part.

Pin Configurations

100-Pin TQFP

DDQ

SSQ

DDQ

NC
V

DDQ

SSQ

DDQ

SSQ

DDQ

NC
V

DDQ

SSQ

DDQ

CLK

BWE

ADSP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

BYTE A

BYTE C

ADV

ADSC

MODE

BYTE B

BYTE D

CY7C1214F

Document #: 38-05434 Rev. *A

Page 3 of 15

Pin Descriptions

Name

TQFP

I/O

Description

A0, A1, A

37,36,32,

33,34,35,

44,45,46,

47,48,81,

82,99,100

Input-

Synchronous

Address Inputs used to select one of the 32K address locations. Sampled at the

rising edge of the CLK if ADSP or ADSC is active LOW, and CE

, and

are

sampled active. A

[1:0]

feed the 2-bit counter.

93,94,

95,96

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes

to the SRAM. Sampled on the rising edge of CLK.

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

CLK, a global write is conducted (ALL bytes are written, regardless of the values on

[A:D]

and BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a Byte Write.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device. ADSP is ignored if CE

is HIGH.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O

pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins

are three-stated, and act as input data pins. OE is masked during the first clock of a

Read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and ADSC

are both asserted, only ADSP is recognized. ASDP is ignored when CE

is deasserted

HIGH

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A

[1:0]

are also loaded into the burst counter. When ADSP and ADSC are

both asserted, only ADSP is recognized.

Input-

Asynchronous

ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a

non-time-critical "sleep" condition with data integrity preserved. For normal operation,

this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQs

52,53,56,

57,58,59,

62,63,68,

69,72,73,

74,75,78,

79,2,3,6,

7,8,9,12,

13,18,19,

22,23,24,

25,28,29,

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained in

the memory location specified by the addresses presented during the previous clock

rise of the read cycle. The direction of the pins is controlled by OE. When OE is

asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a

three-state condition.

15,41,

65, 91

Power

Supply

Power supply inputs to the core of the device.

17,40,

67,90

Ground

Ground for the core of the device.

CY7C1214F

Document #: 38-05434 Rev. *A

Page 4 of 15

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

the clock rise (t

CDV

) is 7.5 ns (117-MHz device).

The CY7C1214F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486TM

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is

user-selectable, and is determined by sampling the MODE

input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.
Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All Writes are simplified with on-chip

synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

is HIGH.

Single Read Accesses
A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE

, CE

, and CE

are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if

the access is initiated by ADSC, the write inputs must be

deasserted during this first cycle). The address presented to

the address inputs is latched into the address register and the

burst counter/control logic and presented to the memory core.

If the OE input is asserted LOW, the requested data will be

available at the data outputs a maximum to t

CDV

after clock

rise. ADSP is ignored if CE

is HIGH.

Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are

satisfied at clock rise: (1) CE

, CE

are all asserted

active, and (2) ADSP is asserted LOW. The addresses

presented are loaded into the address register and the burst

inputs (GW, BWE, and BW[A:D]) are ignored during this first

clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

write) on the next clock rise, the appropriate data will be

latched and written into the device. Byte Writes are allowed.

During byte writes, BWA controls DQA and BWB controls

DQB, BWC controls DQC, and BWD controls DQD. All I/Os

are three-stated during a Byte Write. Since this is a common

I/O device, the asynchronous OE input signal must be

deasserted and the I/Os must be three-stated prior to the

presentation of data to DQs. As a safety precaution, the data

lines are three-stated once a Write cycle is detected,

regardless of the state of OE.

Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE

, CE

, and CE

are all asserted

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the Write input signals (GW, BWE, and

BW[A:D]) indicate a write access. ADSC is ignored if ADSP is

active LOW.
The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the

memory core. The information presented to DQs will be written

into the specified address location. Byte Writes are allowed.

During Byte Writes, BWA controls DQA, BWB controls DQB,

BWC controls DQC, and BWD controls DQD. All I/Os are

three-stated when a write is detected, even a byte write. Since

this is a common I/O device, the asynchronous OE input signal

must be deasserted and the I/Os must be three-stated prior to

the presentation of data to DQs. As a safety precaution, the

data lines are three-stated once a write cycle is detected,

regardless of the state of OE.

Burst Sequences
The CY7C1214F provides an on-chip two-bit wraparound

burst counter inside the SRAM. The burst counter is fed by

A[1:0], and can follow either a linear or interleaved burst order.

The burst order is determined by the state of the MODE input.

A LOW on MODE will select a linear burst sequence. A HIGH

on MODE will select an interleaved burst order. Leaving

MODE unconnected will cause the device to default to a inter-

leaved burst sequence.

DDQ

4,11,20,

27,54,61,

70,77

I/O Power

Supply

Power supply for the I/O circuitry.

SSQ

5,10,21,55

,60,71,76

I/O Ground

Ground for the I/O circuitry.

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to

or left floating selects interleaved burst sequence. This is a strap pin and should

remain static during device operation. Mode Pin has an internal pull-up.

1,14,16,30

,38,39,42,

43,49,50,

51,66,80

No Connects. Not Internally connected to the die.

Pin Descriptions

(continued)

Name

TQFP

I/O

Description

CY7C1214F

Document #: 38-05434 Rev. *A

Page 5 of 15

Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CEs, ADSP, and ADSC must remain

inactive for the duration of t

ZZREC

after the ZZ input returns

LOW.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

Second

Address

Third

Address

Fourth

Address

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

DDZZ

Snooze mode standby current

ZZ > V

0.2V

ZZS

Device operation to ZZ

ZZ > V

0.2V

CYC

ZZREC

ZZ Recovery time

ZZ < 0.2V

CYC

ZZI

ZZ Active to snooze current

This parameter is sampled

CYC

RZZI

ZZ Inactive to exit snooze current

This parameter is sampled

Truth Table

[2, 3, 4, 5, 6]

Cycle Description

Address

Used

ZZ ADSP

ADSC

ADV WRITE

CLK

Deselected Cycle,

Power-down

None

L-H Three-State

Deselected Cycle,

Power-down

None

L-H Three-State

Deselected Cycle,

Power-down

None

L-H Three-State

Deselected Cycle,

Power-down

None

L-H Three-State

Deselected Cycle,

Power-down

None

L-H Three-State

Snooze Mode, Power-down

None

Three-State

Read Cycle, Begin Burst

External

L-H Q

Read Cycle, Begin Burst

External

L-H Three-State

Write Cycle, Begin Burst

External

L-H D

Notes:

2. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW

, BW

) and BWE = L or GW= L. WRITE = H when all Byte Write enable signals

(BW

, BW

), BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

[A: D]

. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is

a don't care for the remainder of the Write cycle

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a Read cycle all data bits are three-state when OE

is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)

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