32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C1299A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05138 Rev. *C
Revised May 14, 2003
Features
Fast clock speed: 100 and 83 MHz
Fast access times: 5.0/6.0 ns max.
Single clock operation
Single 3.3V 5% and +5% power supply V
CC
Separate V
CCQ
for output buffer
Two chip enables for simple depth expansion
Address, data input, CE1, CE2, PTX, PTY, WEX, WEY,
and data output registers on-chip
Concurrent Reads and Writes
Two bidirectional data buses
Can be configured as separate I/O
Pass-through feature
Asynchronous output enables (OEX, OEY)
LVTTL-compatible I/O
Self-timed Write
Automatic power-down
176-pin TQFP package
Functional Description
The CY7C1299A SRAM integrates 32,768 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1299A allows the user to concurrently perform
Reads, Writes, or pass-through cycles in combination on the
two data ports. The two address ports (AX, AY) determine the
read or write locations for their respective data ports (DQX,
DQY).
All input pins except output enable pins (OEX, OEY) are gated
by registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, depth-expansion chip enables (CE1, CE2),
pass-through controls (PTX and PTY), and read-write control
(WEX and WEY). The pass-through feature allows data to be
passed from one port to the other, in either direction. The PTX
input must be asserted to pass data from port X to port Y. The
PTY will likewise pass data from port Y to port X. A
pass-through operation takes precedence over a read
operation.
For the case when AX and AY are the same, certain protocols
are followed. If both ports are read, the reads occur normally.
If one port is written and the other is read, the read from the
array will occur before the data is written. If both ports are
written, only the data on DQY will be written to the array.
The CY7C1299A operates from a +3.3V power supply. All
inputs and outputs are LVTTL compatible. These dual I/O, dual
address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffers, SNA switches
and shared memory applications.
The CY7C1299A needs one extra cycle after power for proper
power-on reset. The extra cycle is needed after V
CC
is stable
on the device. This device is available in a 176-pin TQFP
package.
Note:
1.
For 32K x 36 devices, AX and AY are 15-bit-wide buses.
Logic Block Diagram
[1]
O E y#
C E2
C E1#
O E y#
C E2
C E1#
CY7C1299A
Document #: 38-05138 Rev. *C
Page 2 of 11
Package Description
Selection Guide
-100
-83
Unit
Maximum Access Time
5.0
6.0
ns
Maximum Operating Current
500
430
mA
Maximum CMOS Standby Current
100
100
mA
176-pin TQFP
132
VSS
45
VSS
Notes:
1. AX17 and AY17 at pins 141 and 140 are for 256K x 36 devices only
.
For 128K x 36 devices, pins 141 and 140 are VSS.
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
133
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
VCCQ
DQY35
DQX35
VSS
VSS
AY5
AX5
VSS
VCC
AX14
AY14
VCCQ
VSS
DQX1
DQY1
VSS
DQX0
DQY0
AX13
AY13
AX12
AY12
AX11
AY11
AX10
AY10
AY4
AX4
AY3
AX3
AY2
AX2
AY1
AX1
AY0
AX0
DQY34
DQX34
DQX20
DQY20
VSS
VCCQ
DQX21
DQY21
DQX22
DQY22
VSS
VCCQ
DQX23
DQY23
DQX24
DQY24
VSS
VCCQ
DQX25
DQY25
DQX26
DQY26
VSS
VCC
DQY27
DQX27
DQY28
DQX28
VSS
VCCQ
DQY29
DQX29
DQY30
DQX30
VSS
VCCQ
DQY31
DQX31
DQY32
DQX32
VSS
VCCQ
DQY33
DQX33
VSS
VSS
DQX15
DQY15
VCCQ
VSS
DQX14
DQY14
DQX13
DQY13
VCCQ
VSS
DQX12
DQY12
DQX11
DQY11
VCCQ
VSS
DQX10
DQY10
DQX9
DQY9
VCC
VSS
DQY8
DQX8
DQY7
DQX7
VCCQ
VSS
DQY6
DQX6
DQY5
DQX5
VCCQ
VSS
DQY4
DQX4
DQY3
DQX3
VCCQ
VSS
DQY2
DQX2
VSS
VSS
VSS
VCCQ
DQY18
DQX18
AX6
AY6
AX7
AY7
VCC
VSS
AX8
AY8
AX9
VCC
VSS
DQX16
DQY16
VSS
DQX17
DQY17
AY9
AX17*
AY17*
PTY#
PTX#
W
EY#
W
EX#
CE2X
CE1X#
OEY#
OEX#
VSS
NC
NC
NC
VSS
NC
NC
CLK
DQY19
DQX19
AX16
AY16
AX15
AY15
CE2Y
CE1Y#
NC
NC
NC
NC
NC
CE
1#
NC
NC
NC
NC
NC
CY7C1299A
Document #: 38-05138 Rev. *C
Page 3 of 11
Pin Definitions
Name
I/O
Description
AX0
AX14
Input-
Synchronous
Synchronous Address Inputs of Port X: Do not allow address pins to float.
AY0
AY14
Input-
Synchronous
Synchronous Address Inputs of Port Y: Do not allow address pins to float.
WEX
Input-
Synchronous
Read Write of Port X: WEX signal is a synchronous input that identifies whether the current loaded
cycle is a Read or Write operation.
WEY
Input-
Synchronous
Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current loaded
cycle is a Read or Write operation.
PTX
Input-
Synchronous
Pass-through of Port X: PTX signal is synchronous input that enables passing Port X input to Port Y
output.
PTY
Input-
Synchronous
Pass-through of Port Y: PTY signal is synchronous input that enables passing Port Y input to Port X
output.
OEX
Input
Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH, the
DQXx pins are in high-impedance state.
OEY
Input
Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH, the
DQYx pins are in high impedance state.
DQX0
DQX35
Input/
Output
Data Inputs/Outputs of Port X: Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
DQY0
DQY35
Input/
Output
Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
CLK
Input-
Synchronous
Clock: This is the clock input to this device. Except for OEX and OEY, timing references of the address, data
in, and all control signals for the device are made with respect to the rising edge of CLK.
CE1
Input-
Synchronous
Synchronous Active Low Chip Enable: CE1 sampled HIGH at the rising edge of clock initiates a
deselect cycle.
CE2
Input-
Synchronous
Synchronous Active High Chip Enable: CE2 sampled LOW at the rising edge of clock initiates a
deselect cycle.
VCC
Supply
Power Supply: +3.3V 5% and +5%.
VSS
Ground
Ground: GND.
VSS
Ground
Ground: GND. No chip current flows through these pins. However, user needs to connect GND to these
pins.
VCCQ
I/O Supply
Output Buffer Supply: +3.3V 5% and +5%.
NC
No Connect: These signals are not internally connected. User can connect them to V
CC
, V
SS
, or any
signal lines or simply leave them floating.
Cycle Description Truth Table
[2, 3, 4, 5, 6, 7, 8, 9]
Operation
CE1
CE2
WEX
WEY
PTX
PTY
Deselect Cycle
H
X
X
X
X
X
Deselect Cycle
X
L
X
X
X
X
Write PORT X
L
H
0
X
X
X
Write PORT Y
L
H
X
0
X
X
Pass-Through from X to Y
L
H
X
X
0
X
Pass-Through from Y to X
L
H
X
X
X
0
read PORT X
L
H
1
X
1
1
read PORT Y
L
H
X
1
1
1
Notes:
2.
X means "don't care." H means logic HIGH. L means logic LOW.
3.
All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4.
OEX and OEY must be asserted to avoid bus contention during Write and Pass-Through cycles. For a Write and Pass-Through operation following a Read
operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data hold time.
5.
Operation number 36 can be used in any combination.
6.
Operation number 4 and 7, 3 and 8, 7 and 8 can be combined.
7.
Operation number 5 can not be combined with operation number 7 or 8 because Pass-Through operation has higher priority over a Read operation.
8.
Operation number 6 can not be combined with operation number 7 or 8 because Pass-Through operation has higher priority over a Read operation.
9.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
CY7C1299A
Document #: 38-05138 Rev. *C
Page 4 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... -
55C to +125C
Ambient Temperature with
Power Applied
.................................................... -
10C to +85C
Supply Voltage on V
CC
Relative to GND
.........-
0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[10]
....................................-
0.5V to V
CCQ
+ 0.5V
DC Input Voltage
[10]
................................-
0.5V to V
CCQ
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 1601V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
[11]
V
CC
/V
CCQ
[12,21,22]
Com'l
0C to +70C
3.3V 5%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
Vcc
Power Supply Voltage
3.135
3.465
V
Vcc
Q
I/O Supply Voltage
3.135
3.465
V
V
OH
Output HIGH Voltage
Vcc = Min., I
OH
=
4.0 mA
2.4
V
V
OL
Output LOW Voltage
Vcc = Min., I
OL
= 8.0 mA
0.4
V
V
IH
Input HIGH Voltage
[13]
2.0
Vcc
+
0.5V
V
V
IL
Input LOW Voltage
[14]
-
0.5
0.8
V
I
X
Input Load Current
GND
V
IN
Vcc
Q
-
5
5
A
I
OZ
Output Leakage Current
GND
V
IN
Vcc
Q,
Output Disabled
-
5
5
A
I
CC
Vcc Operating Supply
Vcc
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
10-ns cycle, 100 MHz
500
mA
12-ns cycle, 83MHz
430
mA
I
SB
Automatic CE
Power-down
Current--CMOS Inputs
Max. Vcc, Device Deselected
[
15
]
,
V
IN
0.3V or V
IN
> Vcc
Q
0.3V,
f = f
MAX
= 1/t
CYC
10-ns cycle, 100 MHz
140
mA
12-ns cycle, 83MHz
120
mA
Capacitance
[16]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
Vcc = 3.3V,
Vcc
Q
= 3.3V
8
pF
C
CLK
Clock Input Capacitance
9
pF
C
I/O
Input/Output Capacitance
8
pF
Notes:
10. Minimum voltage equals 2.0V for pulse duration less than 20 ns.
11.
T
A
is the case temperature.
12. Power supply ramp up should be monotonic.
13. Overshoot: V
IH
+6.0V for t
t
KC
/2.
14. Undershoot:
V
IL
2.0V for t
t
KC
/2.
15. "Device Deselected" means the device is in power-down mode as defined in the truth table.
16. Tested initially and after any design or process change that may affect these parameters.
CY7C1299A
Document #: 38-05138 Rev. *C
Page 5 of 11
AC Test Loads and Waveforms
[17]
Thermal Resistance
[16]
Parameter
Description
Test Conditions
TQFP Typ.
Unit
JA
Thermal Resistance (Junction
to Ambient)
(@200 lfm) Single-layer printed circuit board
40
C/W
JC
Thermal Resistance (Junction
to Ambient)
(@200 lfm) Four-layer printed circuit board
35
C/W
JA
Thermal Resistance (Junction
to Board)
Bottom
23
C/W
JC
Thermal Resistance (Junction
to Case)
Top
9
C/W
Switching Characteristics
Over the Operating Range
[17, 18, 19]
Parameter
Description
-100
-83
Unit
Min.
Max.
Min.
Max.
Clock
t
KC
Clock cycle time
10
12
ns
t
KH
Clock HIGH time
3.5
4.0
ns
t
KL
Clock LOW time
3.5
4.0
ns
Output times
t
KQ
Clock to output valid
5.0
6.0
ns
t
KQX
Clock to output invalid
1.5
1.5
ns
t
KQLZ
Clock to output in Low-Z
[20]
0
0
ns
t
KQHZ
Clock to output in High-Z
[20]
3.0
3.0
ns
t
OEQ
OEX/OEY to output valid
5.0
6.0
ns
t
OELZ
OEX/OEY to output in Low-Z
[20]
0
0
ns
t
OEHZ
OEX/OEY to output in High-Z
[20]
3.0
3.0
ns
Set-up times
tS
Addresses, Controls and Data In
1.8
2.0
ns
Hold times
tH
Addresses, Controls and Data In
0.5
0.5
ns
Notes:
17. Overshoot: VIH (AC) <Vcc + 1.5V for t < tTCYC/2; undershoot: VIL(AC) <0.5V for t < tTCYC/2; power-up: VIH <2.6V and Vcc <2.4V and VccQ < 1.4V for t<200
ms.
18. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured
200 mV from steady-state
voltage.
19. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Please refer to waveform (d).
22. The ground level at the start of "power on" on the Vcc pins should be no greater than 200 mV.
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
OUTPUT
R
L
= 50
Z
0
= 50
V
TH
= 1.5V
Vcc
Q
ALL INPUT PULSES
Vcc
Q
GND
90%
10%
90%
10%
1 V/ns
1 V/ns
Vccmin
Vcctyp
t
PU = 200us
For proper RESET
bring Vcc down to 0V
(c)
(d)
(b)
(a)
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