256K X 36 Dual I/O, Dual Address Synchronous SRAM
CY7C1301A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document # 38-05076 Rev. *C
Revised January 19, 2003
Features
Fast Clock Speed: 100 and 83 MHz
Fast Access Times: 5.0/6.0 ns Max.
Single Clock Operation
Single 3.3V 5% and +5% power supply VCC
Separate V
CCQ
for output buffer
Two Chip Enables for simple depth expansion
Address, Data Input, CE1X, CE2X, CE1Y, CE2Y, PTX,
PTY, WEX, WEY, and Data Output Registers On-Chip
Concurrent Reads and Writes
Two bidirectional Data Buses
Can be configured as separate I/O
Pass-Through feature
Asynchronous Output Enables (OEX, OEY)
LVTTL-Compatible I/O
Self-Timed write
Automatic power-down
176-Pin TQFP Package
Functional Description
The CY7C1301A SRAM integrates 262,144 x 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1301A allows the user to concurrently perform
reads, writes, or pass-through cycles in combination on the
two data ports. The two address ports (AX, AY) determine the
read or write locations for their respective data ports (DQX,
DQY).
All input pins except Output Enable pins (OEX, OEY) are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, depth-expansion Chip Enables
(CE1X, CE2X, CE1Y and CE2Y), Pass-Through controls (PTX
and PTY), and Read-Write control (WEX and WEY).
The pass-through feature allows data to be passed from one
port to the other, in either direction. The PTX input must be
asserted to pass data from port X to port Y. The PTY will
likewise pass data from port Y to port X. A pass-through
operation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols
are followed. If both ports are read, the reads occur normally.
If one port is written and the other is read, the read from the
array will occur before the data is written. If both ports are
written, only the data on DQY will be written to the array.
The CY7C1301A operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible. These dual I/O,
dual address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffers, SNA switches
and shared memory applications.
The CY7C1301A device needs one extra cycle after power for
proper power on reset. The extra cycle is needed after V
CC
is
stable on the device. This device is available in a 176-pin
TQFP package.
Note:
1.
For 256 36 device, AX and AY are 18-bit-wide buses.
Data In
Register
OEX#
*AX
256K/128K x 9 x 4
SRAM Array
DQX
CLK
18/17
CE1X#
CE2X
Address
Register
Address
Register
Write X
Register
Write
Driver
Sensing
Amplifiers
Sensing
Amplifiers
Write
Driver
Write Y
Register
Pass-Through
PTX
Register
Data In
Register
Output
Register
Output
Register
Chip Enable
Register
Chip Enable
Register
DQY
WEX#
PTX#
AY*
WEY#
PTY#
PTX
Register
CLK
18/17
OEY#
CE1Y#
CE2Y
Chip Enable
Register
Chip Enable
Register
Logic Block Diagram
[1]
CY7C1301A
Document # 38-05076 Rev. *C
Page 2 of 13
.
Selection Guide
-100
-83
Unit
Maximum Access Time
5.0
6.0
ns
Maximum Operating Current
500
430
mA
Maximum CMOS Standby Current
140
120
mA
Pin Configuration
132
VSS
45
VSS
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
133
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
V
CCQ
DQ
Y
3
5
DQ
X
3
5
VSS
VSS
AY5
AX5
VSS
VC
C
AX14
AY14
V
CCQ
VSS
DQ
X
1
DQ
Y
1
VSS
DQ
X
0
DQ
Y
0
AX13
AY13
AX12
AY12
AX11
AY11
AX10
AY10
AY4
AX4
AY3
AX3
AY2
AX2
AY1
AX1
AY0
AX0
DQ
Y
3
4
DQ
X
3
4
DQX20
DQY20
VSS
VCCQ
DQX21
DQY21
DQX22
DQY22
VSS
VCCQ
DQX23
DQY23
DQX24
DQY24
VSS
VCCQ
DQX25
DQY25
DQX26
DQY26
VSS
VCC
DQY27
DQX27
DQY28
DQX28
VSS
VCCQ
DQY29
DQX29
DQY30
DQX30
VSS
VCCQ
DQY31
DQX31
DQY32
DQX32
VSS
VCCQ
DQY33
DQX33
VSS
VSS
DQX15
DQY15
VCCQ
VSS
DQX14
DQY14
DQX13
DQY13
VCCQ
VSS
DQX12
DQY12
DQX11
DQY11
VCCQ
VSS
DQX10
DQY10
DQX9
DQY9
VCC
VSS
DQY8
DQX8
DQY7
DQX7
VCCQ
VSS
DQY6
DQX6
DQY5
DQX5
VCCQ
VSS
DQY4
DQX4
DQY3
DQX3
VCCQ
VSS
DQY2
DQX2
VSS
VSS
VSS
V
CCQ
DQ
Y
1
8
DQ
X
1
8
AX6
AY6
AX7
AY7
VC
C
VSS
AX8
AY8
AX9
VC
C
VSS
DQ
X
1
6
DQ
Y
1
6
VSS
DQ
X
1
7
DQ
Y
1
7
AY9
AX17*
AY17*
PTY#
PTX#
WEY#
WEX#
CE
2X
CE
1X
#
OEY#
OEX#
VSS
NC
NC
NC
VSS
NC
NC
CLK
DQ
Y
1
9
DQ
X
1
9
AX16
AY16
AX15
AY15
CE
2Y
CE
1Y
#
176-pin TQFP
CY7C1301A
Document # 38-05076 Rev. *C
Page 3 of 13
Pin Definitions (176-pin TQFP)
Pin Name
I/O
Pin Description
AX0AX1
7
Input-
Synchronous
Synchronous Address Inputs of Port X: Do not allow address pins to float.
AY0AY17
Input-
Synchronous
Synchronous Address Inputs of Port Y: Do not allow address pins to float.
WEX
Input-
Synchronous
Read Write of Port X: WEX signal is a synchronous input that identifies whether the current
loaded cycle is a Read or Write operation.
WEY
Input-
Synchronous
Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current
loaded cycle is a Read or Write operation.
PTX
Input-
Synchronous
Pass-Through of Port X: PTX signal is a synchronous input that enables passing Port X input
to Port Y output.
PTY
Input-
Synchronous
Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input
to Port X output.
OEX
Input
Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is
HIGH, the DQXx pins are in high-impedance state.
OEY
Input
Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is
HIGH, the DQYx pins are in high-impedance state.
DQX0
DQX35
Input/
Output
Data Inputs/Outputs of Port X: Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
DQY0
DQY35
Input/
Output
Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
CLK
Input-
Synchronous
Clock: This is the clock input to this device. Except for OEX and OEY, all timing references
of the address, data in, and all control signals for the device are made with respect to the rising
edge of CLK.
CE1X
Input-
Synchronous
Synchronous Active LOW Chip Enable Port X: CE1X is used with CE2X to enable Port X
of this device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for
Port X.
CE2X
Input-
Synchronous
Synchronous Active HIGH Chip Enable Port X: CE2X is used with CE1X to enable Port X
of this device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for
Port X.
CE1Y
Input-
Synchronous
Synchronous Active LOW Chip Enable Port Y: CE1Y is used with CE2Y to enable Port Y
of this device. CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for
Port Y.
CE2Y
Input-
Synchronous
Synchronous Active HIGH Chip Enable Port Y: CE2Y is used with CE1Y to enable Port Y
of this device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for
Port Y.
V
CC
Supply
Power Supply: +3.3V 5% and +5%.
V
SS
Ground
Ground: GND.
V
SS
Ground
Ground: GND. No chip current flows through these pins. However, user needs to connect
GND to these pins. Pins 140 and 141 are V
SS
for 128K 36 device.
V
CCQ
I/O Supply
Output Buffer Supply: +3.3V 5% and +5%.
NC
No Connect: These signals are not internally connected. User can connect them to V
CC
, V
SS
,
or any signal lines or simply leave them floating.
CY7C1301A
Document # 38-05076 Rev. *C
Page 4 of 13
Cycle Description Truth Table
[2, 3, 4, 5, 6, 7, 8, 9]
Operation
CE1X
CE2X
CE1Y
CE2Y
WEX
WEY
PTX
PTY
Deselect Cycle
H
X
H
X
X
X
X
X
Deselect Cycle
X
L
X
L
X
X
X
X
Write Port X
L
H
X
X
0
X
X
X
Write Port Y
X
X
L
H
X
0
X
X
Pass-through from X to Y
L
H
L
H
X
X
0
X
Pass-through from Y to X
L
H
L
H
X
X
X
0
Read Port X
L
H
X
X
1
X
1
1
Read Port Y
X
X
L
H
X
1
1
1
Notes:
2.
X means "Don't Care." H means logic HIGH. L means logic LOW.
3.
All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4.
OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For a Write and Pass-through operation following a READ
operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data
hold time.
5.
Operation number 36 can be used in any combination.
6.
Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined.
7.
Operation number 5 can not be combined with operation number 7 or 8 because Pass-through operations have higher priority over a Read operation.
8.
Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operations have higher priority over a Read operation.
9.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
CY7C1301A
Document # 38-05076 Rev. *C
Page 5 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... -
55C to +125C
Ambient Temperature with
Power Applied
.................................................... -
10C to +85C
Supply Voltage on V
DD
Relative to GND
.........-
0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[10]
....................................-
0.5V to V
CCQ
+ 0.5V
DC Input Voltage
[10]
................................-
0.5V to V
CCQ
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >1601V
(per MIL-STD-883, Method 3015)
Latch-Up Current ................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
[11]
V
DD
/V
DDQ
(12)
Commercial
0C to +70C
3.3V 5%
Electrical Characteristics
Over the Operating Range
Parame-
ter
Description
Test Conditions
Min.
Max.
Unit
V
DD
Power Supply Voltage
3.135
3.465
V
V
DDQ
I/O Supply Voltage
3.135
3.465
V
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
=
4.0 mA
2.4
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
0.4
V
V
IH
Input HIGH
Voltage
[13]
2.0
V
CC
+
0.5V
V
V
IL
Input LOW Voltage
[14]
-
0.5
0.8
V
I
X
Input Load Current
GND
V
IN
V
DDQ
-
5
5
A
I
OZ
Output Leakage
Current
GND
V
IN
V
DDQ,
Output Disabled
-
5
5
A
I
CC
V
DD
Operating
Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
10.0 ns cycle 100 MHz
500
mA
12.0 ns cycle 83 MHz
430
mA
I
SB
Automatic CE
Power-Down
Current--CMOS
Inputs
Max. V
DD
, Device Deselected
[15]
,
V
IN
0.3V or V
IN
> V
DDQ
0.3V,
f = 0
10.0 ns cycle100 MHzs
140
mA
12.0 ns cycle 83MHz
120
mA
Capacitance
[18]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= 3.3V,
V
CCQ
= 3.3V
8
pF
C
CLK
Clock Input Capacitance
9
pF
C
I/O
Input/Output Capacitance
8
pF
Notes:
10. Minimum voltage equals 2.0V for pulse duration less than 20 ns.
11.
T
A
is the case temperature.
12. Power supply ramp up should be monotonic.
13. Overshoot: V
IH
+6.0V for t
t
KC /2
.
14. Undershoot:V
IL
2.0V for t
t
KC /2
.
15. "Device Deselected" means the device is in Power-down mode as defined in the truth table.
16. Tested initially and after any design or process change that may affect these parameters.
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