1K x 8 Dual-Port Static Ram
fax id: 5200
CY7C130/CY7C131
CY7C140/CY7C141
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
May 1989 Revised March 27, 1997
1CY 7C14 0
Features
True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
1K x 8 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 15 ns
Low operating power: I
CC
= 90 mA (max.)
Fully asynchronous operation
Automatic power-down
Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
INT flag for port-to-port communication
Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and
52-pin TQFP
Pin-compatible and functionally equivalent to
IDT7130/IDT7140
Functional Description
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave du-
al-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being ac-
cessed by the other port. INT is an interrupt flag indicating that
data has been placed in a unique location (3FF for the left port
and 3FE for the right port). An automatic power-down feature
is controlled independently on each port by the chip enable
(CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC and
PQFP.
s
Notes:
1.
CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2.
Open drain outputs: pull-up resistor required
Logic Block Diagram
Pin Configurations
C130-1
C130-2
13
14
15
16
17
18
19
20
21
22
23
26
27
28
32
31
30
29
33
36
35
34
24
25
GND
1
2
3
4
5
6
7
8
9
10
11
38
39
40
44
43
42
41
45
48
47
46
12
37
R/W
L
CE
L
BUSY
L
INT
L
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
CE
R
R/W
R
BUSY
R
INT
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
V
CC
DIP
Top View
7C130
7C140
R/W
L
BUSY
L
CE
L
OE
L
A
9L
A
0L
A
0R
A
9R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
BUSY
R
INT
L
INT
R
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
[1]
[2]
[2]
CY7C130/CY7C131
CY7C140/CY7C141
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 3.5V to +7.0V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Notes:
3.
15 and 25-ns version available only in PLCC/PQFP packages.
4.
Shaded area contains preliminary information.
5.
T
A
is the "instant on" case temperature
Pin Configuration
(continued
)
1
Top View
PLCC
OE
R
A
0R
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2
52 51 50 49 48 47
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
C130-3
7C131
7C141
46
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
1415 16 17 18 19 20 21 22 23 24 25 26
52 5150 49 48 47
45 44 43 42 41 40
Top View
PQFP
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
C130-4
7C131
7C141
Selection Guide
7C131-15
[3,4]
7C141-15
7C131-25
[3]
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Maximum Access Time (ns)
15
25
30
35
45
55
Maximum Operating
Current (mA)
Com'l/Ind
190
170
170
120
90
90
Military
170
120
120
Maximum Standby
Current (mA)
Com'l/Ind
75
65
65
45
35
35
Military
65
45
45
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
5V 10%
Industrial
40
C to +85
C
5V 10%
Military
[5]
55
C to +125
C
5V 10%
CY7C130/CY7C131
CY7C140/CY7C141
3
]
Electrical Characteristics
Over the Operating Range
[6]
7C131-15
[3,4]
7C141-15
7C130-30
[3]
7C131-25,30
7C140-30
7C141-25,30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45,55
7C131-45,55
7C140-45,55
7C141-45,55
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min. Max.
Min.
Max.
Unit
V
OH
Output HIGH
Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
2.4
2.4
V
V
OL
Output LOW
Voltage
I
OL
= 4.0 mA
0.4
0.4
0.4
0.4
V
I
OL
= 16.0 mA
[7]
0.5
0.5
0.5
0.5
V
IH
Input HIGH Voltage
2.2
2.2
2.2
2.2
V
V
IL
Input LOW Voltage
0.8
0.8
0.8
0.8
V
I
IX
Input Leakage
Current
GND < V
I
< V
CC
5
+5
5
+5
5
+5
5
+5
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
5
+5
5
+5
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[8, 9]
V
CC
= Max.,
V
OUT
= GND
350
350
350
350
mA
I
CC
V
CC
Operating
Supply Current
CE = V
IL
,
Outputs Open,
f = f
MAX
[10]
Com'l
190
170
120
90
mA
Mil
170
120
I
SB1
Standby Current
Both Ports,
TTL Inputs
CE
L
and CE
R
>
V
IH
, f = f
MAX
[10]
Com'l
75
65
45
35
mA
Mil
65
45
I
SB2
Standby Current
One Port,
TTL Inputs
CE
L
or CE
R
> V
IH
,
Active Port Out-
puts Open,
f = f
MAX
[10]
Com'l
135
115
90
75
mA
Mil
115
90
I
SB3
Standby Current
Both Ports,
CMOS Inputs
Both Ports CE
L
and CE
R
> V
CC
0.2V,
V
IN
> V
CC
0.2V
or V
IN
< 0.2V, f = 0
Com'l
15
15
15
15
mA
Mil
15
15
I
SB4
Standby Current
One Port,
CMOS Inputs
One Port CE
L
or
CE
R
> V
CC
0.2V,
V
IN
> V
CC
0.2V
or V
IN
< 0.2V,
Active Port Outputs
Open,
f = f
MAX
[10]
Com'l
125
105
85
70
mA
Mil
105
85
Notes:
6.
See the last page of this specification for Group A subgroup testing information.
7.
BUSY and INT pins only.
8.
Duration of the short circuit should not exceed 30 seconds.
9.
This parameter is guaranteed but not tested.
10. At f=f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
RC
and using AC Test Waveforms input levels of GND to 3V.
Capacitance
[9]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
15
pF
C
OUT
Output Capacitance
10
pF
CY7C130/CY7C131
CY7C140/CY7C141
4
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[6,11]
7C131-15
[3,4]
7C141-15
7C130-25
[3]
7C131-25
7C140-25
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
25
30
ns
t
AA
Address to Data Valid
[12]
15
25
30
ns
t
OHA
Data Hold from Address Change
0
0
0
ns
t
ACE
CE LOW to Data Valid
[12]
15
25
30
ns
t
DOE
OE LOW to Data Valid
[12]
10
15
20
ns
t
LZOE
OE LOW to Low Z
[9,13, 14]
3
3
3
ns
t
HZOE
OE HIGH to High Z
[9,13, 14]
10
15
15
ns
t
LZCE
CE LOW to Low Z
[9,13, 14]
3
5
5
ns
t
HZCE
CE HIGH to High Z
[9,13, 14]
10
15
15
ns
t
PU
CE LOW to Power-Up
[9]
0
0
0
ns
t
PD
CE HIGH to Power-Down
[9]
15
25
25
ns
WRITE CYCLE
[15]
t
WC
Write Cycle Time
15
25
30
ns
t
SCE
CE LOW to Write End
12
20
25
ns
t
AW
Address Set-Up to Write End
12
20
25
ns
t
HA
Address Hold from Write End
2
2
2
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
R/W Pulse Width
12
15
25
ns
t
SD
Data Set-Up to Write End
10
15
15
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
HZWE
R/W LOW to High Z
[14]
10
15
15
ns
t
LZWE
R/W HIGH to Low Z
[14]
0
0
0
ns
Notes:
11.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30-pF load capacitance.
12. AC Test Conditions use V
OH
= 1.6V and V
OL
= 1.4V.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5pF as in part (b) of AC Test Loads
. Transition is measured 500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write
3.0V
5V
OUTPUT
R1 893
R2
347
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
90%
10%
5 ns
5ns
5V
OUTPUT
R1 893
R2
347
5 pF
INCLUDING
JIGAND
SCOPE
(a)
(b)
OUTPUT
1.40V
Equivalent to:
THVENIN EQUIVALENT
5V
281
30
pF
BUSY
OR
INT
BUSY Output Load
(CY7C130/CY7C131 ONLY)
10%
C130-5
C130-6
ALL INPUT PULSES
250
CY7C130/CY7C131
CY7C140/CY7C141
5
BUSY/INTERRUPT TIMING
t
BLA
BUSY LOW from Address Match
15
20
20
ns
t
BHA
BUSY HIGH from Address Mismatch
[16]
15
20
20
ns
t
BLC
BUSY LOW from CE LOW
15
20
20
ns
t
BHC
BUSY HIGH from CE HIGH
[16]
15
20
20
ns
t
PS
Port Set Up for Priority
5
5
5
ns
t
WB
[17]
R/W LOW after BUSY LOW
0
0
0
ns
t
WH
R/W HIGH after BUSY HIGH
13
20
30
ns
t
BDD
BUSY HIGH to Valid Data
15
25
30
ns
t
DDD
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
ns
t
WDD
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
t
WINS
R/W to INTERRUPT Set Time
15
25
25
ns
t
EINS
CE to INTERRUPT Set Time
15
25
25
ns
t
INS
Address to INTERRUPT Set Time
15
25
25
ns
t
OINR
OE to INTERRUPT Reset Time
[16]
15
25
25
ns
t
EINR
CE to INTERRUPT Reset Time
[16]
15
25
25
ns
t
INR
Address to INTERRUPT Reset Time
[16]
15
25
25
ns
Notes:
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B's address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Switching Characteristics
Over the Operating Range
[6,11]
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
35
45
55
ns
t
AA
Address to Data Valid
[12]
35
45
55
ns
t
OHA
Data Hold from Address Change
0
0
0
ns
t
ACE
CE LOW to Data Valid
[12]
35
45
55
ns
t
DOE
OE LOW to Data Valid
[12]
20
25
25
ns
t
LZOE
OE LOW to Low Z
[9,13, 14]
3
3
3
ns
t
HZOE
OE HIGH to High Z
[9,13, 14]
20
20
25
ns
t
LZCE
CE LOW to Low Z
[9,13, 14]
5
5
5
ns
t
HZCE
CE HIGH to High Z
[9,13, 14]
20
20
25
ns
t
PU
CE LOW to Power-Up
[9]
0
0
0
ns
t
PD
CE HIGH to Power-Down
[9]
35
35
35
ns
Switching Characteristics
Over the Operating Range
[6,11]
(continued)
7C131-15
[3,4]
7C141-15
7C130-25
[3]
7C131-25
7C140-25
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
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