Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

2K x 16 Dual-Port Static RAM

CY7C133
CY7C143

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-06036 Rev. *B

Revised June 22, 2004

Features

· True dual-ported memory cells which allow

simultaneous reads of the same memory location

· 2K x 16 organization
· 0.65-micron CMOS for optimum speed/power
· High-speed access: 25/35/55 ns
· Low operating power: I

= 150 mA (typ.)

· Fully asynchronous operation
· Master CY7C133 expands data bus width to 32 bits or

more using slave CY7C143

· BUSY output flag on CY7C133; BUSY input flag on

CY7C143

· Available in 68-pin PLCC

Functional Description

The CY7C133 and CY7C143 are high-speed CMOS 2K by 16

dual-port static RAMs. Two ports are provided permitting

independent access to any location in memory. The CY7C133

can be utilized as either a stand-alone 16-bit dual-port static

RAM or as a master dual-port RAM in conjunction with the

CY7C143 slave dual-port device in systems requiring 32-bit or

greater word widths. It is the solution to applications requiring

shared or buffered data, such as cache memory for DSP,

bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),

Write Enable (R/W

, R/W

), and Output Enable (OE).

BUSY signals that the port is trying to access the same

location currently being accessed by the other port. An

automatic power-down feature is controlled independently on

each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.

Note:

CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.

R/W

LUB

10L

R/W

RUB

R/W

LUB

R/W

RUB

I/O

15L

ARBITRATION

LOGIC

(CY7C133 ONLY)

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

BUSY

[1]

CONTROL

I/O

R/W

LLB

R/W

RLB

I/O

R/W

RLB

10R

I/O

15R

BUSY

[ ]

I/O

R/W

LLB

Logic Block Diagram

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 2 of 13

Pin Configuration

I/O

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

Top View

68-Pin LCC/PLCC

60
59
58
57
56
55
54
53
52
51
50
49
48

3132 33 34 35 36 37 38 39 40 41 42 43

5 4 3 2 1 68

66 65 64 63 62 61

BUSY

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I/O

15L

GND

I/O

2728 29 30

9 8 7 6

47
46
45
44

I/O

25
26

10L

I/
O

R/W

I/O

GND

R/W

I/O

I/
O

I/O

7C133
7C143

Selection Guide

7C133-25

7C143-25

7C133-35

7C143-35

7C133-55

7C143-55

Unit

Maximum Access Time

Typical Operating Current I

170

160

150

Typical Standby Current for I

SB1

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 3 of 13

Architecture

The CY7C133 (master) and CY7C143 (slave) consist of an

array of 2K words of 16 bits each of dual-port RAM cells, I/O

and address lines, and control signals (CE, OE, R/W). These

control pins permit independent access for reads or writes to any

location in memory. To handle simultaneous writes/reads to the same

location, a BUSY pin is provided on each port. The CY7C133 and

CY7C143 have an automatic power-down feature controlled by CE.

Each port is provided with its own output enable control (OE), which

allows data to be read from the device.

Functional Description

Write Operation
Data must be set up for a duration of t

before the rising edge

of R/W in order to guarantee a valid write. A write operation is

controlled by either the R/W pin (see Write Cycle No. 1 waveform) or

the CE pin (see Write Cycle No. 2 waveform). Two R/W pins (R/W

and R/W

) are used to separate the upper and lower bytes of IO.

Required inputs for non-contention operations are summarized in

Table 1.
If a location is being written to by one port and the opposite

port attempts to read that location, a port-to-port flow-through

delay must occur before the data is read on the output;

otherwise the data read is not deterministic. Data will be valid

on the port t

DDD

after the data is presented on the other port.

Read Operation
When reading the device, the user must assert both the OE

and CE pins. Data will be available t

ACE

after CE or t

DOE

after OE is

asserted.

Busy
The CY7C133 (master) provides on-chip arbitration to resolve

simultaneous memory location access (contention). Table 2

shows a summery of conditions where BUSY is asserted. If both

ports' CEs are asserted and an address match occurs within t

each other, the busy logic will determine which port has access. If t

is violated, one port will definitely gain permission to the location, but

which one is not predictable. BUSY will be asserted t

BLA

after an

address match or t

BLC

after CE is taken LOW. The results of all eight

arbitration possibilities are summarized in Table 3. BUSY is an open

drain output and requires a pull-up resistor.

One master and as many slaves as necessary may be

connected in parallel to expand the data bus width in 16 bit

increments. The BUSY output of the master is connected to the

BUSY input of the slave. Writing to slave devices must be delayed

until after the BUSY input has settled (t

BLC

or t

BLA

). Otherwise, the

slave chip may begin a write cycle during a contention

situation.

Flow-Through Operation
The CY7C133/143 has a flow-through architecture that facili-

tates repeating (actually extending) an operation when a

BUSY is received by a losing port. The BUSY signal should be

interpreted as a NOT READY. If a BUSY to a port is active, the

port should wait for BUSY to go inactive, and then extend the

operation it was performing for another cycle. The timing

diagram titled, "Timing waveform with port to port delay" illus-

trates the case where the right port is writing to an address and

the left port reads the same address. The data that the right

port has just written flows through to the left, and is valid either

DDD

after the falling edge of the write strobe of the left port, or

DDD

after the data being written becomes stable.

Data Retention Mode
The CY7C133/143 is designed with battery backup in mind.

Data retention voltage and supply current are guaranteed over

temperature. The following rules insure data retention:

1. Chip enable (CE) must be held HIGH during data retention, with-

in V

to V

0.2V.

2. CE must be kept between V

0.2V and 70% of V

during the power-up and power-down transitions.

3. The RAM can begin operation >t

after V

reaches the

minimum operating voltage (4.5V).

Note:

CE = V

, V

= GND to V

, T

= 25°C. This parameter is guaranteed but not tested.

Timing

Parameter

Test Conditions

[2]

Max.

Unit

ICC

DR1

@ VCC

= 2V

1.5

Data Retention Mode

4.5V

2.0V

to V

0.2V

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 4 of 13

Table 1. Non-Contending Read/Write Control

Control

I/O

Operation

R/W

I/O

High Z

Deselected: Power-Down

Data In

Write to Both Bytes

Data In

Data Out

Write Lower Byte, Read Upper Byte

Data Out

Data In

Read Lower Byte, Write Upper Byte

Data In

High Z

Write to Lower Byte

High Z

Data In

Write to Upper Byte

Data Out

Read to Both Bytes

High Z

High Impedance Outputs

Table 2. Address BUSY Arbitration

Inputs

Outputs

Function

Address

BUSY

No Match

Normal

Match

Normal

Match

Normal

Match

Note 3

Write Inhibit

[4]

32-Bit Master/Slave Dual-Port Memory Systems

Table 3. Arbitration Results

Case

Port

Winning Port

Result

Left

Right

Read

Both ports read

Read

Both ports read

Read

Write

L port reads OK R port write inhibited

Read

Write

R port writes OK L port data may be invalid

Write

Read

L port writes OK R port data may be invalid

Write

Read

R port reads OK L port write inhibited

Write

L port writes OK R port write inhibited

Write

R port writes OK L port write inhibited

Notes:

The loser of the port arbitration will receive BUSY = "L" (BUSY

or BUSY

= "L"). BUSY

and BUSY

cannot both be LOW simultaneously.

Writes are inhibited to the left port when BUSY

is LOW. Writes are inhibited to the right port when BUSY

is LOW.

LEFT

RIGHT

R/W

BUSY

R/W

BUSY

R/W

BUSY

R/W

CY7C133

CY7C143

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 5 of 13

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)
Storage Temperature

..................................... -

C to +150

Ambient Temperature with

Power Applied

.................................................. -

C to +125

Supply Voltage to Ground Potential

(Pin 48 to Pin 24)

.................................................-

0.5V to +7.0V

DC Voltage Applied to Outputs

in High-Z State

.....................................................-

0.5V to +7.0V

DC Input Voltage

.................................................-

3.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA

Operating Range

Range

Ambient Temperature

Commercial

C to +70

5V ± 10%

Industrial

C to +85

5V ± 10%

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

7C133-25

7C143-25

Unit

Min.

Typ.

Max.

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= 4.0 mA

0.4

= 16.0 mA

[5]

0.5

Input HIGH Voltage

2.2

Input LOW Voltage

0.8

Input Leakage Current

GND < V

< V

Output Leakage Current

GND < V

< V

, Output Disabled

Output Short Circuit Current

[6, 7]

= Max., V

OUT

= GND

200

Operating Supply Current

CE = V

Outputs Open, f = f

MAX

[8]

Com'l

170

250

Ind.

170

290

SB1

Standby Current Both Ports, TTL

Inputs

and CE

> V

, f = f

MAX

[8]

Com'l

Ind.

SB2

Standby Current One Port, TTL

Inputs

or CE

> V

, Active Port

Outputs Open, f = f

MAX

[8]

Com'l

100

140

Ind.

100

160

SB3

Standby Current Both Ports,

CMOS Inputs

Both Ports CE

and CE

> V

0.2V, V

> V

0.2V or V

0.2V, f = 0

Com'l

Ind.

SB4

Standby Current One Port,

CMOS Inputs

One Port CE

or CE

> V

0.2V,

> V

0.2V or

< 0.2V, Active Port Outputs Open,

f = f

MAX

[8]

Com'l

120

Ind.

140

Electrical Characteristics

Over the Operating Range (continued)

Parameter

Description

Test Conditions

7C133-35

7C143-35

7C133-55

7C143-55

Unit

Min. Typ. Max. Min.

Typ.

Max.

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= 4.0 mA

0.4

= 16.0 mA

[5]

0.5

Input HIGH Voltage

2.2

Input LOW Voltage

0.8

Input Leakage Current GND < V

< V

Notes:

BUSY pin only.

Duration of the short circuit should not exceed 30 seconds.

Tested initially and after any design or process changes that may affect these parameters.

At f=f

MAX

, address and data inputs are cycling at the maximum frequency of read cycle of 1/t

and using AC Test Waveforms input levels of GND to 3V.

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 6 of 13

Output Leakage

Current

GND < V

< V

, Output Disabled

Output Short Circuit

Current

[6, 7]

= Max., V

OUT

= GND

200

Operating Supply

Current

CE = V

Outputs Open, f = f

MAX

[8]

Com'l

160

230

150

220

Ind.

160

260

150

250

SB1

Standby Current Both

Ports, TTL Inputs

and CE

> V

, f = f

MAX

[8]

Com'l

Ind.

SB2

Standby Current One

Port, TTL Inputs

or CE

> V

, Active Port

Outputs Open, f = f

MAX

[8]

Com'l

125

110

Ind.

140

125

SB3

Standby Current Both

Ports, CMOS Inputs

Both Ports CE

and CE

- 0.2V, V

> V

0.2V

or V

< 0.2V, f = 0

Com'l

Ind.

SB4

Standby Current One

Port, CMOS Inputs

One Port CE

or CE

> V

0.2V, V

> V

0.2V or

< 0.2V, Active Port

Outputs Open, f = f

MAX

[8]

Com'l

105

Ind.

120

105

Capacitance

[7]

Parameter

Description

Test Conditions

Max.

Unit

Input Capacitance

= 25

C, f = 1 MHz, V

= 5.0V

OUT

Output Capacitance

AC Test Loads and Waveforms

Electrical Characteristics

Over the Operating Range (continued)

Parameter

Description

Test Conditions

7C133-35

7C143-35

7C133-55

7C143-55

Unit

Min. Typ. Max. Min.

Typ.

Max.

3.0V

OUTPUT

R1893

347

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

OUTPUT

R1893

347

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

1.40V

Equivalent to:

TH ÉVENIN EQUIVALENT

281

30 pF

BUSY

INT

BUSY Output Load

(CY7C133 ONLY)

10%

ALL INPUT PULSES

250

< 3 ns

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 7 of 13

Switching Characteristics

Over the Operating Range

[9]

Parameter

Description

7C133-25

7C143-25

7C133-35

7C143-35

7C133-55

7C143-55

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Read Cycle
t

Read Cycle Time

Address to Data Valid

[10]

OHA

Data Hold from Address Change

ACE

CE LOW to Data Valid

[10]

DOE

OE LOW to Data Valid

[10]

LZOE

OE LOW to Low Z

[11, 12,13]

HZOE

OE HIGH to High Z

[11, 12,13]

LZCE

CE LOW to Low Z

[11, 12,13]

HZCE

CE HIGH to High Z

[11, 12,13]

CE LOW to Power-Up

[13]

CE HIGH to Power-Down

[13]

Write Cycle

[14]

Write Cycle Time

SCE

CE LOW to Write End

Address Set-up to Write End

Address Hold from Write End

Address Set-up to Write Start

PWE

R/W Pulse Width

Data Set-up to Write End

Data Hold from Write End

HZWE

R/W LOW to High Z

[12,13]

LZWE

R/W HIGH to Low Z

[12,13]

Busy/Interrupt Timing (for master CY7C133)
t

BLA

BUSY Low from Address Match

BHA

BUSY High from Address Mismatch

BLC

BUSY Low from CE LOW

BHC

BUSY High from CE HIGH

WDD

Write Pulse to Data Delay

[15]

DDD

Write Data Valid to Read Data Valid

[15]

BDD

BUSY High to Valid Data

[16]

Note 16

Arbitration Priority Set Up Time

[17]

Busy Timing (for slave CY7C143)
t

Write to BUSY

[18]

Write Hold After BUSY

[19]

WDD

Write Pulse to Data Delay

[20]

DDD

Write Data Valid to Read Data Valid

[20]

Notes:

Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified

OH,

and 30-pF load capacitance.

10. AC Test Conditions use V

= 1.6V and V

= 1.4V.

11. At any given temperature and voltage condition for any given device, t

LZCE

is less than t

HZCE

and t

LZOE

is less than t

HZOE

12. t

LZCE

, t

LZWE

, t

HZOE

, t

LZOE

, t

HZCE

and t

HZWE

are tested with C

= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.

13. This parameter is guaranteed but not tested.

14. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal

can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of "Read with BUSY, Master: CY7C133."

16. t

BDD

is a calculated parameter and is greater of 0,t

WDD

(actual) or t

DDD

(actual).

17. To ensure that the earlier of the two ports wins.

18. To ensure that write cycle is inhibited during contention.

19. To ensure that a write cycle is completed after contention.

20. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of "Read with Port-to-port Delay."

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 9 of 13

Timing Waveform of Read with Port-to-port Delay No. 4 (for slave CY7C143)

[24, 25, 26]

Write Cycle No. 1 (OE Three-States Data I/Os - Either Port)

[17, 27]

Notes:

24. Assume BUSY input at V

for the writing port and at V

for the reading port.l

25. Write cycle parameters should be adhered to in order to ensure proper writing.

26. Device is continuously enabled for both ports.

27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or t

HZWE

+ t

to allow the data I/O pins to enter high

impedance and for data to be placed on the bus for the required t

Switching Waveforms

(continued)

VALID

DDD

MATCH

R/W

INR

DOUT

VALID

WDD

ADDRESS

DATA VALID

HIGH IMPEDANCE

SCE

PWE

HZOE

Either Port

R/W

ADDRESS

DATA

OUT

CY7C133
CY7C143

Document #: 38-06036 Rev. *B

Page 12 of 13

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

2K x 16 Master Dual-Port SRAM

Speed

(ns)

Ordering Code

Package

Name

Package Type

Operating

Range

CY7C133-25JC

J81