512K x 36/1M x 18 Pipelined SRAM
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Document #: 38-05240 Rev. *A
Revised November 20, 2002
380CV25
Features
Fast clock speed: 250, 225, 200, 167 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns
Optimal for depth expansion
Single 2.5V
5% power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down available using ZZ mode or CE
deselect
Available in 119-ball bump BGA, 165-ball FBGA and
100-pin TQFP packages
JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced single-layer
polysilicon, triple-layer metal technology. Each memory cell
consists of six transistors.
The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data (DQa,b,c,d) and the data par-
ity (DQPa,b,c,d) outputs, enabled by OE, are also asynchro-
nous.
DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and
DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each
are of 8 bits wide in the case of DQ and 1 bit wide in the case
of DP.
Addresses and chip enables are registered with either address
status processor (ADSP) or address status controller (ADSC)
input pins. Subsequent burst addresses can be internally gen-
erated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. BWa con-
trols DQa and DPa. BWb controls DQb and DPb. BWc controls
DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc,
and BWd can be active only with BWE being LOW. GW being
LOW causes all bytes to be written. Write pass-through capa-
bility allows written data available at the output for the next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
All inputs and outputs of the CY7C1380CV25 and the
CY7C1382CV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
250 MHz
225 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
2.8
3.0
3.4
ns
Maximum Operating Current
350
325
300
275
mA
Maximum CMOS Standby Current
70
70
70
70
mA
Shaded areas contain advance information.
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