512K x 36 / 1M x 18 Pipelined DCD SRAM
CY7C1387BV25
CY7C1386BV25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05253 Rev. *A
Revised January 18, 2003
Features
Fast clock speed: 200,167, 150, 133 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.0, 3.4, 3.8, 4.2 ns
Optimal for depth expansion
2.5V 5% power supply
Common data inputs and data outputs
Double-cycle Deselect
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down available using ZZ mode or CE
deselect
High-density, high-speed packages
JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1386BV25 and CY7C1387BV25 SRAMs integrate
1,048,576 18 and 524,288 36 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control
inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data (DQ
a,b,c,d
) and the data parity
(DP
a,b,c,d
) outputs, enabled by OE, are also asynchronous.
DQ
a,b,c,d
and DP
a,b,c,d
apply to CY7C1386BV25 and DQ
a,b
and DP
a,b
apply to CY7C1387BV25. a, b, c, d each are of eight
bits wide in the case of DQ and one bit wide in the case of DP.
Addresses and chip enables are registered with either address
status processor (ADSP) or address status controller (ADSC)
input pins. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPd. BWd controls DQd-DQd and DPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. Write
pass-through capability allows written data available at the
output for the immediately next Read cycle. This device also
incorporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
The CY7C1386BV25/CY7C1387BV25 are both double-cycle
deselect parts. All inputs and outputs of the CY7C1386BV25
and the CY7C1387BV25 are JEDEC-standard JESD8-5-
compatible.
Selection Guide
200 MHz
167 MHz
150 MHz
133 MHz
Unit
Maximum Access Time
3.0
3.4
3.8
4.2
ns
Maximum Operating Current
Commercial
280
230
190
160
mA
Maximum CMOS Standby Current
30
30
30
30
mA
PDF 
ZIP
