PRELIMINARY
2M x 36/4M x 18/1M x 72 Pipelined SRAM
CY7C1480V33
CY7C1482V33
CY7C1486V33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05283 Rev. *A
Revised January 18, 2003
Features
Fast clock speed: 250, 200, and 167 MHz
Provide high-performance 3-1-1-1 access rate
Fast access time: 2.6, 3.0, and 3.4 ns
Optimal for depth expansion
Single 3.3V 5% and +5% power supply V
DD
Separate V
DDQ
for 3.3V or 2.5V
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down for portable applications
High-density, high-speed packages
JTAG boundary scan for BGA packaging version
Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1480V33 and CY7C1482V33).
165-ball FBGA and 209-ball BGA(CY7C1486V33)
packages will be offered on an opportunity basis
(Please contact Cypress sales or marketing)
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1480V33, CY7C1482V33, and CY7C1486V33
SRAMs integrate 2,097,152 36/4,194,304 18/1,048,576
72 SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by
a positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), burst control inputs (ADSC, ADSP, and
ADV), Write Enables (BW
a
, BW
b
, BW
c
, BW
d
, and BWE), and
Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQ
x
) and the data
parity (DP
x
) outputs, enabled by OE, are also asynchronous.
DQ
a,b,c,d
and DP
a,b,c,d
apply to CY7C1480V33, DQ
a,b,c,d,e,f,g,h
and
DP
a,b,c,d,e,f,g,h
apply to
CY7C1486V33, and DQ
a,b
and
DP
a,b
apply to CY7C1482V33. a, b, c, d, e, f, g, and h each are
eight bits wide in the case of DQ and one bit wide in the case
of DP.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycles. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BW
a
controls DQ
a
and DP
a
. BW
b
controls DQ
b
and DP
b
. BW
c
controls DQ
c
and DP
c
. BW
d
controls DQ
d
and DP
d
. BW
e
controls DQ
e
and DP
e
. BW
f
controls DQ
f
and DP
f
. BW
g
controls DQ
g
and DP
g
. BW
h
controls DQ
h
and DP
h
. BW
a
,
BW
b
, BW
c
, BW
d
, BW
e
, BW
f
, BW
g
, and BW
h
can be active only
with BWE LOW. GW LOW causes all bytes to be written. Write
passthrough capability allows written data available at the
output for the immediate-next Read cycle. This device also
incorporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1480V33, CY7C1482V33,
and CY7C1486V33 are JEDEC-standard JESD8-5-
compatible.
Selection Guide
CY7C1480V33-250
CY7C1482V33-250
CY7C1486V33-250
CY7C1480V33-200
CY7C1482V33-200
CY7C1486V33-200
CY7C1480V33-167
CY7C1482V33-167
CY7C1486V33-167
Unit
Maximum Access Time
2.6
3.0
3.4
ns
Maximum Operating Current
TBD
TBD
TBD
mA
Maximum CMOS Standby
Current
TBD
TBD
TBD
mA
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