PRELIMINARY
64K x 8 Static RAM
CY7C1512
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
June 1996 Revised October 1996
1CY 7C15 12
Features
High speed
-- t
AA
= 15 ns
CMOS for optimum speed/power
Low active power
-- 770 mW
Low standby power
-- 28 mW
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
The CY7C1512 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
1
), an active
HIGH chip enable (CE
2
), an active LOW output enable (OE),
and three-state drivers. This device has an automatic pow-
er-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
15
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
Logic Block Diagram
Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
64K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
CE
1
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15
17
18
GND
NC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
1512-1
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
1512-2
A
6
A
7
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
TSOP I
Top View
NC
Selection Guide
7C1512-15
7C1512-20
7C1512-25
7C1512-35
7C1512-70
Maximum Access Time (ns)
15
20
25
35
70
Maximum Operating
Current (mA)
Commercial
140
130
120
110
110
Maximum CMOS
Standby Current (mA)
Commercial
5
5
5
5
5
CY7C1512
PRELIMINARY
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
.....................................0.5V to V
CC
+0.5V
DC Input Voltage
[1]
..................................0.5V to V
CC
+0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MILSTD883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Industrial
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range
[3]
Parameter
Description
Test Conditions
7C1512-15
7C1512-20
7C1512-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+
0.3
2.2
V
CC
+
0.3
2.2
V
CC
+
0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
A
I
OZ
Output Leakage Current
GND < V
I
< V
CC
,Output Disabled
5
+5
5
+5
5
+5
A
I
OS
Output Short Circuit Current
[4]
V
CC
= Max., V
OUT
= GND
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
140
130
120
mA
I
SB1
Automatic CE
PowerDown Current
-- TTL Inputs
Max. V
CC
, CE
1
> V
IH
or
CE
2
< V
IL
, V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
40
30
30
mA
I
SB2
Automatic CE
PowerDown Current
-- CMOS Inputs
Max. V
CC
, CE
1
> V
CC
0.3V,
or CE
2
< 0.3V, V
IN
> V
CC
0.3V,
or V
IN
< 0.3V, f=0
5
5
5
mA
Parameter
Description
Test Conditions
7C1512-35
7C1512-70
Unit
Min.
Max.
Min.
Max.
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
[1]
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
A
I
OZ
Output Leakage Current
GND < V
I
< V
CC
, Output Disabled
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[4]
V
CC
= Max., V
OUT
= GND
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
110
110
mA
I
SB1
Automatic CE
Power-Down Current
-- TTL Inputs
Max. V
CC
, CE
1
> V
IH
or CE
2
< V
IL
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
25
25
mA
I
SB2
Automatic CE
Power-Down Current
-- CMOS Inputs
Max. V
CC
, CE
1
> V
CC
0.3V, or CE
2
<
0.3V, V
IN
> V
CC
0.3V, or V
IN
< 0.3V, f=0
5
5
mA
Notes:
1.
V
IL
(min.) = -2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "instant on" case temperature.
3.
See the last page of this specification for Group A subgroup testing information.
4.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C1512
PRELIMINARY
3
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
9
pF
C
OUT
Output Capacitance
9
pF
AC Test Loads and Waveforms
Switching Characteristics
[3, 6]
Over the Operating Range
Parameter
Description
7C1512-15
7C1512-20
7C1512-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
15
20
25
ns
t
AA
Address to Data Valid
15
20
25
ns
t
OHA
Data Hold from Address Change
3
3
5
ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
15
20
25
ns
t
DOE
OE LOW to Data Valid
7
8
10
ns
t
LZOE
OE LOW to Low Z
0
0
0
ns
t
HZOE
OE HIGH to High Z
[7, 8]
7
8
10
ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[8]
3
3
5
ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[7, 8]
7
8
10
ns
t
PU
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
0
0
0
ns
t
PD
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
15
20
25
ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time
15
20
25
ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End
12
15
20
ns
t
AW
Address Set-Up to Write End
12
15
20
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
12
15
20
ns
t
SD
Data Set-Up to Write End
8
10
15
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[8]
3
3
5
ns
t
HZWE
WE LOW to High Z
[7, 8]
7
8
10
ns
5.
Tested initially and after any design or process changes that may affect these parameters.
6.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
8.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9.
The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
1512-3
1512-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
<3ns
< 3 ns
OUTPUT
R1 480
R1 480
R2
255
R2
255
167
Equivalent to:
TH VENIN EQUIVALENT
1.73V
CY7C1512
PRELIMINARY
4
Switching Characteristics
[3, 6]
Over the Operating Range (continued)
Parameter
Description
7C1512-35
7C1512-70
Unit
Min.
Min.
Min.
Min.
READ CYCLE
t
RC
Read Cycle Time
35
70
ns
t
AA
Address to Data Valid
35
70
ns
t
OHA
Data Hold from Address Change
5
5
ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
35
70
ns
t
DOE
OE LOW to Data Valid
15
15
ns
t
LZOE
OE LOW to Low Z
0
0
ns
t
HZOE
OE HIGH to High Z
[7, 8]
15
15
ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[8]
5
5
ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[7, 8]
15
15
ns
t
PU
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
0
0
ns
t
PD
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
35
70
ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time
35
70
ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End
25
60
ns
t
AW
Address Set-Up to Write End
25
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
25
60
ns
t
SD
Data Set-Up to Write End
20
55
ns
t
HD
Data Hold from Write End
0
0
ns
t
LZWE
WE HIGH to Low Z
[8]
5
5
ns
t
HZWE
WE LOW to High Z
[7, 8]
15
15
ns
Switching Waveforms
Notes:
10. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
11.
WE is HIGH for read cycle.
Read Cycle No. 1
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
1512-5
ADDRESS
DATA OUT
[10, 11]
CY7C1512
PRELIMINARY
5
Notes:
12. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
13. Data I/O is high impedance if OE = V
IH
.
14. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
Read Cycle No. 2 (OE Controlled)
1512-6
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
ICC
ISB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
[11, 12]
1512-7
t
WC
DATA VALID
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[13, 14]
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