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16K x 4 Static RAM
CY7C164
CY7C166
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05025 Rev. **
Revised August 24, 2001
66
Features
High speed
-- 15 ns
Output enable (OE) feature (CY7C166)
CMOS for optimum speed/power
Low active power
-- 633 mW
Low standby power
-- 110 mW
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C164 and CY7C166 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
three-state drivers. The CY7C166 has an active LOW Output
Enable (OE) feature. Both devices have an automatic power-
down feature, reducing the power consumption by 65% when
deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW (and the
Output Enable (OE) is LOW for the CY7C166). Data on the
four input/output pins (I/O
0
through I/O
3
) is written into the
memory location specified on the address pins (A
0
through
A
13
).
Reading the device is accomplished by taking Chip Enable
(CE) LOW (and OE LOW for CY7C166), while Write Enable
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the four data I/O pins.
The I/O pins stay in a high-impedance state when Chip Enable
(CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166).
A die coat is used to insure alpha immunity.
]
OE
CE
GND
Logic Block Diagram
Pin Configurations
256 x 64 x 4
ARRAY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
19
22
21
20
Top View
DIP
7C164
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
9
A
11
A
10
A
12
A
13
COLUMN
DECODER
ROW
DE
CODE
R
S
E
N
S
E AM
PS
INPUT BUFFER
POWER
DOWN
WE
(OE)
(7C166 ONLY)
I/O
3
CE
I/O
2
I/O
1
I/O
0
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
CE
GND
WE
V
CC
A
4
A
3
A
2
A
1
I/O
3
I/O
2
I/O
1
I/O
0
A
0
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
7C164
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
3
I/O
2
I/O
1
I/O
0
A
0
GND
NC
NC
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
7C166
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
3
I/O
2
I/O
1
I/O
0
A
0
NC
CE
12
13
12
13
C1644
C1643
C1642
C1661
Selection Guide
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA)
115
115
105
105
Maximum Standby Current (mA)
20
20
20
20
CY7C164
CY7C166
Document #: 38-05025 Rev. **
Page 2 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65C to +150C
Ambient Temperature with
Power Applied............................................. 55C to +125C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
............................................ 0.5V to +7.0V
DC Input Voltage
[1]
........................................ 0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0C to +70C
5V
10%
Electrical Characteristics
Over the Operating Range
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25, 35
7C166-25, 35
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH
Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
2.4
V
V
OL
Output LOW
Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
2.2
V
CC
2.2
V
CC
V
V
IL
Input LOW
Voltage
[1]
0.5
0.8
0.5
0.8
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
5
+5
5
+5
5
+5
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
5
+5
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[2]
V
CC
= Max.,
V
OUT
= GND
350
350
350
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA
115
115
105
mA
I
SB1
Automatic CE
Power-Down Current
[3]
Max. V
CC
, CE > V
IH,
Min. Duty Cycle = 100%
40
40
20
mA
I
SB2
Automatic CE
Power-Down Current
[3]
Max. V
CC
,
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V
or V
IN
< 0.3V
20
20
20
mA
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz,
V
CC
= 5.0V
10
pF
C
OUT
Output Capacitance
10
pF
Notes:
1.
Minimum voltage is equal to 3.0V for pulse durations less than 30 ns.
2.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3.
A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
4.
Tested initially and after any design or process changes that may affect these parameters.
CY7C164
CY7C166
Document #: 38-05025 Rev. **
Page 3 of 9
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
5V
OUTPUT
R1 481
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
C1645
C1646
167
Switching Characteristics
Over the Operating Range
[5]
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
20
25
35
ns
t
AA
Address to Data Valid
15
20
25
35
ns
t
OHA
Output Hold from Address Change
3
5
5
5
ns
t
ACE
CE LOW to Data Valid
15
20
25
35
ns
t
DOE
OE LOW to Data Valid
7C166
10
10
12
15
ns
t
LZOE
OE LOW to Low Z
7C166
3
3
3
3
ns
t
HZOE
OE HIGH to High Z
7C166
8
8
10
12
ns
t
LZCE
CE LOW to Low Z
[6]
3
5
5
5
ns
t
HZCE
CE HIGH to High Z
[6, 7]
8
8
10
15
ns
t
PU
CE LOW to Power-Up
0
0
0
0
ns
t
PD
CE HIGH to Power-Down
15
20
20
20
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
15
20
20
25
ns
t
SCE
CE LOW to Write End
12
15
20
25
ns
t
AW
Address Set-Up to Write End
12
15
20
25
ns
t
HA
Address Hold from Write End
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
ns
t
PWE
WE Pulse Width
12
15
15
20
ns
t
SD
Data Set-Up to Write End
10
10
10
15
ns
t
HD
Data Hold from Write End
0
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[6]
5
5
5
5
ns
t
HZWE
WE LOW to High Z
[6, 7]
7
7
7
10
ns
Notes:
5.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device. These parameters are guaranteed by design and not 100% tested.
7.
t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) in AC Test Loads. Transition is measured
500 mV from steady-state voltage.
8.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C164
CY7C166
Document #: 38-05025 Rev. **
Page 4 of 9
Switching Waveforms
Notes:
9.
WE is HIGH for read cycle.
10. Device is continuously selected, CE = V
IL
. (CY7C166: OE = V
IL
also).
11. Address valid prior to or coincident with CE transition LOW.
12. CY7C166 only: Data I/O will be high-impedance if OE = V
IH
.
Read Cycle No.1
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
C1647
[9, 10]
Read Cycle No. 2
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
7C166
CE
HIGH
V
CC
SUPPLY
CURRENT
C1648
[9, 11]
Write Cycle No. 1 (WE Controlled)
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
HZWE
t
LZWE
t
SD
C1649
DATA
IN
VALID
[8, 12]
CE
WE
DATA IN
DATA I/O
ADDRESS
CY7C164
CY7C166
Document #: 38-05025 Rev. **
Page 5 of 9
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
t
WC
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
C16410
DATA
IN
VALID
[8, 12, 13]
ADDRESS
CE
DATA IN
DATA I/O
WE
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