16K x 1 Static RAM
CY7C167A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05027 Rev. **
Revised August 24, 2001
67A
Features
Automatic power-down when deselected
CMOS for optimum speed/power
High speed
-- 15 ns
Low active power
-- 495 mW
Low standby power
-- 220 mW
TTL-compatible inputs and outputs
Capable of withstanding greater than 2001V electro-
static discharge
V
IH
of 2.2V
Functional Description
The CY7C167A is a high-performance CMOS static RAM or-
ganized as 16,384 words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C167A has an automatic power-down fea-
ture, reducing the power consumption by 67% when
deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DI) is written into the memory location specified on
the address pins (A
0
through A
13
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while (WE) remains HIGH. Under these conditions,
the contents of the location specified on the address pins will
appear on the data output (DO) pin.
The output pin remains in a high-impedance state when Chip
Enable is HIGH, or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
128 x 128
ARRAY
C167A-1
Top View
DIP
A
1
A
2
A
3
A
4
A
0
COLUMN
DECODER
ROW DE
CODER
SEN
SE AM
P
INPUT BUFFER
POWER
DOWN
WE
CE
DO
A
5
DI
A
6
A
9
A
10
A
7
A
8
A
11
A
12
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
7C167A
A
1
A
2
A
3
A
4
A
5
DO
CE
GND
WE
V
CC
A
12
A
11
A
10
C167A-2
A
0
A
9
A
8
A
7
DI
A
6
A
13
20
19
Selection Guide
7C167A-15
7C167A-20
7C167A-25
7C167A-35
7C167A-45
Maximum Access Time (ns)
15
20
25
35
45
Maximum Operating Current (mA)
90
90
90
90
90
CY7C167A
Document #: 38-05027 Rev. **
Page 2 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................-
65
C to +150
C
Ambient Temperature with
Power Applied
..................................................-
55
C to +125
C
Supply Voltage to Ground Potential
(Pin 20 to Pin 10)
................................................ -
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.................................................... -
0.5V to +7.0V
DC Input Voltage
.................................................-
3.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[1]
V
CC
Commercial
0
C to +70
C
5V
10%
Electrical Characteristics
Over the Operating Range
7C167A-15
7C167A-20
7C167A-25
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output High Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
2.4
V
V
OL
Output Low Voltage
V
CC
= Min.,
I
OL
= 12.0 mA, 8.0 mA Mil
0.4
0.4
0.4
V
V
IH
Input High Voltage
2.2
V
CC
2.2
V
CC
2.2
V
CC
V
V
IL
Input Low Voltage
[2]
-
0.5
0.8
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
10
+10
-
10
+10
-
10
+10
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
Output Disabled
-
10
+10
-
10
+10
-
10
+10
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
-
350
-
350
-
350
mA
I
CC
V
CC
Operating
Supply Current
V
CC =
Max., I
OUT
= 0 mA
90
90
90
mA
I
SB
Automatic CE
Power-Down Current
[4]
Max. V
CC
, CE > V
IH
40
40
20
mA
7C167A-35
7C167A-45
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output High Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
V
V
OL
Output Low Voltage
V
CC
= Min.,
I
OL
= 12.0 mA, 8.0 mA Mil
0.4
0.4
V
V
IH
Input High Voltage
2.2
V
CC
2.2
V
CC
V
V
IL
Input Low Voltage
[2]
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
10
+10
-
10
+10
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
Output Disabled
-
10
+10
-
10
+10
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
-
350
-
350
mA
I
CC
V
CC
Operating
Supply Current
V
CC =
Max., I
OUT
= 0 mA
90
90
mA
I
SB
Automatic CE
Power-Down Current
[4]
Max. V
CC
, CE > V
IH
20
20
mA
Notes:
1.
T
A
is the case temperature.
2.
V
IL
min. =
-
3.0V for pulse durations less than 30 ns.
3.
Duration of the short circuit should not exceed 30 seconds.
4.
A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
CY7C167A
Document #: 38-05027 Rev. **
Page 3 of 9
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
10
pF
C
OUT
Output Capacitance
10
pF
C
CE
Chip Enable Capacitance
6
pF
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 329
R2
202
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
5V
OUTPUT
C167A-3
R1 329
R2
202
5 pF
INCLUDING
JIG AND
SCOPE
C167A-4
(a)
(b)
OUTPUT
1.9V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
125
Switching Characteristics
Over the Operating Range
[6]
7C167A-15
7C167A-20
7C167A-25
7C167A-35
7C167A-45
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
20
25
30
ns
t
AA
Address to Data Valid
15
20
25
30
ns
t
OHA
Data Hold from Address Change
5
5
5
5
5
ns
t
ACE
CE LOW to Data Valid
15
20
25
35
45
ns
t
LZCE
CE LOW to Low Z
[7]
5
5
5
5
5
ns
t
HZCE
CE HIGH to High Z
[7, 8]
8
8
10
15
15
ns
t
PU
CE LOW to Power-Up
0
0
0
0
0
ns
t
PD
CE HIGH to Power-Down
15
20
20
20
25
ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time
15
20
20
25
40
ns
t
SCE
CE LOW to Write End
12
15
20
25
30
ns
t
AW
Address Set-Up to Write End
12
15
20
25
30
ns
t
HA
Address Hold from Write End
0
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
0
ns
t
PWE
WE Pulse Width
12
15
15
20
20
ns
t
SD
Data Set-Up to Write End
10
10
10
15
15
ns
t
HD
Data Hold from Write End
0
0
0
0
0
ns
t
HZWE
WE LOW to High Z
[7, 8]
7
7
7
10
15
ns
t
LZWE
WE HIGH to Low Z
[7]
5
5
5
5
5
ns
Notes:
5.
Tested initially and after any design or process changes that may affect these parameters.
6.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7.
At any given temperature and voltage condition, t
HZ
is less than t
LZ
for any given device.
8.
t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C167A
Document #: 38-05027 Rev. **
Page 4 of 9
Switching Waveforms
Notes:
10. WE is high for read cycle.
11. Device is continuously selected, CE = V
IL
.
12. Address valid prior to or coincident with CE transition LOW.
C167A-5
50%
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
50%
DATA VALID
t
RC
t
ACE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZCE
t
PD
CE
HIGH
C167A-6
V
CC
SUPPLY
CURRENT
t
OHA
Read Cycle No. 1
[10, 11]
Read Cycle No. 2
[10, 12]
ADDRESS
DATA OUT
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
HZWE
t
LZWE
t
SD
C167A-7
CE
WE
DATA IN
DATA I/O
ADDRESS
DATA
IN
VALID
Write Cycle No. 1 (WE Controlled)
[9]
CY7C167A
Document #: 38-05027 Rev. **
Page 5 of 9
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
t
WC
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
PWE
t
HA
t
HD
t
HZWE
t
SD
ADDRESS
CE
WE
DATA IN
DATA I/O
t
SA
C167A-8
DATA
IN
VALID
Write Cycle No. 2 (CE Controlled)
[9, 13]
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