32K x 9 Static RAM
CY7C188
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05053 Rev. **
Revised August 24, 2001
88
Features
High speed
-- 15 ns
Automatic power-down when deselected
Low active power
-- 660 mW
Low standby power
-- 140 mW
CMOS for optimum speed/power
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE
features
Functional Description
The CY7C188 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 9 bits. Easy memory expansion is
provided by an active-LOW chip enable (CE
1
), an active-HIGH
chip enable (CE
2
), an active-LOW output enable (OE), and
three-state drivers. The device has an automatic power-down
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking CE
1
and write
enable (WE) inputs LOW and CE
2
input HIGH. Data on the
nine I/O pins (I/O
o
I/O
8
) is then written into the location spec-
ified on the address pins (A
0
A
14
).
Reading from the device is accomplished by taking CE
1
and
OE LOW while forcing WE and CE
2
HIGH. Under these con-
ditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The nine input/output pins (I/O
0
I/O
8
) are placed in a high-im-
pedance state when the device is deselected (CE
1
HIGH or
CE
2
LOW), the outputs are disabled (OE HIGH), or during a
write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C188 is available in standard 300-mil-wide SOJs.
Logic Block Diagram
Pin Configuration
C1881
CE
2
WE
I/O
0
CE
1
I/O
1
I/O
2
I/O
3
I/O
7
I/O
6
I/O
5
I/O
4
I/O
8
I/O
4
A
1
A
2
A
3
A
4
A
5
A
6
COLUMN
DECODER
ROW DE
CODER
SE
N
S
E AM
PS
INPUT BUFFER
POWER
DOWN
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
12
13
25
28
27
26
A
8
A
7
A
6
A
5
A
4
A
3
A
2
WE
V
CC
A
14
A
13
A
9
A
1
NC
I/O
0
CE
1
OE
A
11
32K x 9
ARRAY
A
0
A
11
A
13
A
12
A
14
A
10
29
32
31
30
NC
A
0
GND
I/O
1
I/O
2
I/O
3
CE
2
A
10
A
12
I/O
5
I/O
6
I/O
7
I/O
8
A
8
A
9
A
7
OE
C1882
Selection Guide
7C18815
7C18820
7C18825
7C18835
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA) Commercial
120
170
165
160
Maximum Standby Current (mA)
35
35
35
30
CY7C188
Document #: 38-05053 Rev. **
Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage on V
CC
Relative to GND
(Pin 32 to Pin 16) .......................................... 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................. 0.5V to V
CC
+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
5V
10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter
7C18815
7C18820
7C18825
7C18835
Unit
Description
Test Conditions
Min.
Max
Min.
Max.
Min.
Max.
Min.
Max.
V
OH
Output HIGH
Voltage
V
CC
= Min.,
I
OH
= 4.0 mA
2.4
2.4
2.4
2.4
V
V
OL
Output LOW
Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
0.4
V
V
IH
Input HIGH
Voltage
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
2.2
V
CC
+ 0.3
V
V
IL
Input LOW
Voltage
[1]
0.5
0.8
0.5
0.8
0.5
0.8
0.5
0.8
V
I
IX
Input Load Current
GND
V
I
V
CC
5
+5
5
+5
5
+5
5
+5
A
I
OZ
Output Leakage
Current
GND
V
I
V
CC
,
Output Disabled
5
+5
5
+5
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max.,
V
OUT
= GND
300
300
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
120
170
165
160
mA
I
SB1
Automatic CE
Power-Down
Current--
TTL Inputs
Max. V
CC
, CE
1
V
IH
or CE
2
V
IL
,
V
IN
V
IH
or V
IN
V
IL
,
f = f
MAX
35
35
35
30
mA
I
SB2
Automatic CE
Power-Down
Current
-- CMOS Inputs
Max. V
CC
,
CE
1
V
CC
0.3V or
CE
2
0.3V,
V
IN
V
CC
0.3V
or V
IN
0.3V, f = 0
10
15
15
15
mA
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
: Addresses
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
6
pF
C
IN
: Controls
Input Capacitance
8
pF
C
OUT
Output Capacitance
8
pF
Notes:
1.
Minimum voltage is equal to 2.0V for pulse durations less than 20 ns.
2.
.See the last page of this specification for Group A subgroup testing information.
3.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4.
Tested initially and after any design or process changes that may affect these parameters.
CY7C188
Document #: 38-05053 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
[5, 6]
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
3 ns
3 ns
5V
OUTPUT
R1 481
R2
255
5 pF
INCLUDING
JIGAND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH VENIN EQUIVALENT
ALLINPUTPULSES
C1883
C1884
167
Switching Characteristics
Over the Operating Range
[2, 5]
7C18815
7C18820
7C18825
7C18835
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
20
25
35
ns
t
AA
Address to Data Valid
15
20
25
35
ns
t
OHA
Data Hold from Address Change
3
3
3
3
ns
t
ACE
CE
1
LOW or CE
2
HIGH to Data Valid
15
20
25
35
ns
t
DOE
OE LOW to Data Valid
7
9
10
16
ns
t
LZOE
OE LOW to Low Z
[7]
0
0
3
3
ns
t
HZOE
OE HIGH to High Z
[6,7]
7
9
11
15
ns
t
LZCE
CE
1
LOW or CE
2
HIGH to Low Z
[7]
3
3
3
3
ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High Z
[6, 7]
7
9
11
15
ns
t
PU
CE
1
LOW or CE
2
HIGH to Power-Up
0
0
0
0
ns
t
PD
CE
1
HIGH or CE
2
LOW to Power-Down
15
20
20
20
ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time
15
20
25
35
ns
t
SCE
CE
1
LOW or CE
2
HIGH to Write End
10
15
18
22
ns
t
AW
Address Set-Up to Write End
10
15
20
30
ns
t
HA
Address Hold from Write End
0
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
0
ns
t
PWE
WE Pulse Width
10
15
18
22
ns
t
SD
Data Set-Up to Write End
8
10
10
15
ns
t
HD
Data Hold from Write End
0
0
0
0
ns
t
HZWE
WE LOW to High Z
[6]
0
7
0
7
0
11
0
15
ns
t
LZWE
WE HIGH to Low Z
[6, 7]
3
3
3
3
ns
CY7C188
Document #: 38-05053 Rev. **
Page 4 of 8
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
The internal write time of the memory is defined by the overlap of CE
1
, LOW, CE
2
HIGH, and WE LOW. All three signals must be asserted to initiate a write and any
signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Switching Characteristics
Over the Operating Range
[2, 5]
7C18815
7C18820
7C18825
7C18835
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Switching Waveforms
Read Cycle No. 1
[10,11]
Read Cycle No. 2 (Chip-Enable Controlled)
[11,12,13]
Write Cycle No. 1 (WE Controlled)
[8,13,14,15]
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
C1885
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
1
HIGH
V
CC
SUPPLY
CURRENT
C1886
CY7C188
Document #: 38-05053 Rev. **
Page 5 of 8
Notes:
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Timing parameters are the same for all chip enable signals (CE
1
and CE
2
), so only the timing for CE
1
is shown.
14. Data I/O is high impedance if OE = V
IH
.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in the output state and input signals should not be applied.
Write Cycle No.2 (CE Controlled)
[8,13,14,15]
Write Cycle No. 3 (WE Controlled, OE LOW)
[9,13,15]
Switching Waveforms
(Continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
WE
OE
t
HZOE
C1887
CE
1
DATA
IN
VALID
NOTE 16
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
C1888
CE
1
DATA
IN
VALID
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