PRELIMINARY
18-Mbit QDR-IITM SRAM 2-Word
Burst Architecture
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-05619 Rev. **
Revised July 23, 2004
Features
Separate Independent Read and Write data ports
-- Supports concurrent transactions
200-MHz clock for high bandwidth
2-Word Burst on all accesses
Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 400 MHz) @ 200 MHz
Two input clocks (K and K) for precise DDR timing
-- SRAM uses rising edges only
Two output clocks (C and C) accounts for clock skew
and flight time mismatching
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
Available in x8, x9, x18, and x36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8V (0.1V); I/O V
DDQ
= 1.4V to V
DD
15 17 1.4 mm 1.0-mm pitch FBGA package, 165-ball
(11 15 matrix)
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 2M x 8
CY7C1910BV18 2M x 9
CY7C1312BV18 1M x 18
CY7C1314BV18 512K x 36
Functional Description
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDRTM-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to "turn-around" the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another. In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with two 8-bit words
(CY7C1310BV18) or 9-bit words (CY7C1910BV18) or 18-bit
words (CY7C1312BV18) or 36-bit words (CY7C1314BV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus "turn-arounds."
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
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