PRELIMINARY
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document Number: 38-05621 Rev. **
Revised July 26, 2004
Features
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
250-MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 500 MHz) @ 250 MHz
Two input clocks (K and K) for precise DDR timing
-- SRAM uses rising edges only
Two output clocks (C and C) account for clock skew
and flight time mismatching
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4VV
DD
)
15 x 17 x 1.4 mm 1.0-mm pitch fBGA package,
165 ball (11x15 matrix)
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1316BV18 2M x 8
CY7C1916BV18 2M x 9
CY7C1318BV18 1M x 18
CY7C1320BV18 512K x 36
Functional Description
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1316BV18 and two 9-bit words in the case of
CY7C1916BV18 that burst sequentially into or out of the
device. The burst counter always starts with a "0" internally in
the case of CY7C1316BV18 and CY7C1916BV18. On
CY7C1318BV18 and CY7C1320BV18, the burst counter
takes in the least significant bit of the external address and
bursts two 18-bit words in the case of CY7C1318BV18 and two
36-bit words in the case of CY7C1320BV18 sequentially into
or out of the device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) enable maximum system clocking
and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
TBD
TBD
TBD
mA
Shaded areas contain advance information.
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