64K x 4 Static RAM
with Separate I/O
CY7C192
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05047 Rev. **
Revised August 24, 2001
92
Features
High speed
-- 12 ns
CMOS for optimum speed/power
Low active power
-- 880 mW
Low standby power
-- 220 mW
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C192 is a high-performance CMOS static RAM orga-
nized as 65,536 x 4 bits with separate I/O. Easy memory ex-
pansion is provided by active LOW Chip Enable (CE) and
three-state drivers. It has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and write enable (WE) inputs are both LOW.
Data on the four input pins (I
0
through I
3
) is written into the
memory location specified on the address pins (A
0
through
A
15
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW while the Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the four data output pins.
The output pins stay in high-impedance state when Write En-
able (WE) is LOW, or Chip Enable (CE) is HIGH.
A die coat is used to insure alpha immunity.
GND
28
Logic Block Diagram
Pin Configurations
1024 x 64 x 4
ARRAY
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
10
A
11
A
13
A
12
A
14
A
15
COLUMN
DECODER
ROW DECODE
R
S
E
N
S
E
AM
PS
POWER
DOWN
WE
O
0
CE
O
1
O
2
O
3
4
5
6
7
8
9
10
3 2 1
27
1314151617
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
O
3
O
2
O
1
O
0
A
0
CE
11
12
19
18
A
8
V CC
A
9
A
10
A
11
A
12
A
13
A
14
A
15
I
0
A
4
A
3
A
2
A
1
A
0
I
3
I
2
O
3
O
1
GND
CE
WE
Top View
LCC
12
13
INPUT BUFFER
25
28
27
26
A
14
A
15
I
0
I
1
A
5
I
3
I
2
I
1
A
7
A
6
A
5
O
2
O
0
I
0
I
1
I
2
I
3
7C192 ONLY
A
0
A
9
C1911
C1912
C1913
Selection Guide
7C192-12
7C192-15
7C192-20
7C192-25
Maximum Access Time (ns)
12
15
20
25
Maximum Operating Current (mA)
155
145
135
115
Maximum Standby Current (mA)
30
30
30
30
CY7C192
Document #: 38-05047 Rev. **
Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... -
65
C to +150
C
Ambient Temperature with
Power Applied
.................................................. -
55
C to +125
C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)
.................................................-
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................... -
0.5V to V
CC
+
0.5V
DC Input Voltage
[1]
.................................... -
0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Electrical Characteristics
Over the Operating Range
7C192-12
7C192-15
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+0.3V
2.2
V
CC
+0.3V
V
V
IL
Input LOW Voltage
[1]
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
5
+5
-
5
+5
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
-
5
+5
-
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max., V
OUT
= GND
-
300
-
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.
,
I
OUT
= 0 mA, f = f
MAX
= 1/t
RC
155
145
mA
I
SB1
Automatic CE Power-
Down Current--
TTL Inputs
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
30
30
mA
I
SB2
Automatic CE Power-
Down Current--CMOS
Inputs
Max. V
CC
, CE > V
CC
-
0.3V,
V
IN
> V
CC
-
0.3V or V
IN
< 0.3V,
f = 0
10
10
mA
Notes:
1.
Minimum voltage is equal to
-
2.0V for pulse durations of less than 20 ns.
2.
T
A
is the case temperature.
3.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C192
Document #: 38-05047 Rev. **
Page 3 of 10
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
7C192-20
7C192-25
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+0.3V
2.2
V
CC
+0.3V
V
V
IL
Input LOW Voltage
[1]
-
0.5
0.8
-
3.0
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
5
+5
-
5
+5
A
I
OZ
Output Leakage Current
GND < V
O
< V
CC
, Output Disabled
-
5
+5
-
5
+5
A
I
OS
Output Short Circuit
Current
[3]
V
CC
= Max., V
OUT
= GND
-
300
-
300
mA
I
CC
V
CC
Operating Supply
Current
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
135
115
mA
I
SB1
Automatic CE Power-Down
Current--TTL Inputs
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
30
30
mA
I
SB2
Automatic CE Power-Down
Current--CMOS Inputs
CE > V
CC
0.3V,
V
IN
V
CC
0.3V or V
IN
< 0.3V, f = 0
15
15
mA
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
8
pF
C
OUT
Output Capacitance
10
pF
AC Test Loads and Waveforms
[5]
Notes:
4.
Tested initially and after any design or process changes that may affect these parameters.
5.
t
r
= < 3 ns for the -12 and -15 speeds. T.
r
= < 5 ns for the -20 and slower speeds.
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< t
r
< t
r
5V
OUTPUT
R1 481
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH VENIN EQUIVALENT
ALL INPUT PULSES
C1914
C1915
167
CY7C192
Document #: 38-05047 Rev. **
Page 4 of 10
Switching Characteristics
Over the Operating Range
[6]
7C192-12
7C192-15
7C192-20
7C192-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
12
15
20
25
ns
t
AA
Address to Data Valid
12
15
20
25
ns
t
OHA
Output Hold from
Address Change
3
3
3
3
ns
t
ACE
CE LOW to
Data Valid
12
15
20
25
ns
t
LZCE
CE LOW to
Low Z
[7]
3
3
3
3
ns
t
HZCE
CE HIGH to
High Z
[7,8]
5
7
9
11
ns
t
PU
CE LOW to
Power-Up
0
0
0
0
ns
t
PD
CE HIGH to
Power-Down
12
15
20
25
ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time
12
15
20
25
ns
t
SCE
CE LOW to
Write End
9
10
15
18
ns
t
AW
Address Set-Up to
Write End
9
10
15
20
ns
t
HA
Address Hold from
Write End
0
0
0
0
ns
t
SA
Address Set-Up to
Write Start
0
0
0
0
ns
t
PWE
WE Pulse Width
8
9
15
18
ns
t
SD
Data Set-Up to
Write End
8
9
10
10
ns
t
HD
Data Hold from
Write End
0
0
0
0
ns
t
LZWE
WE HIGH to
Low Z (7C192)
[7]
3
3
3
3
ns
t
HZWE
WE LOW to
High Z (7C192)
[7,8]
7
7
10
11
ns
t
DWE
WE LOW to Data Valid
(7C191)
12
15
20
25
ns
t
ADV
Data Valid to
Output Valid (7C191)
12
15
20
20
ns
t
DCE
CE LOW to Data Valid
(7C191)
12
15
20
25
ns
Notes:
6.
Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 through -25 speeds, timing reference levels of
1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZWE
is less than t
LZWE
for any given device. These parameters are guaranteed by
design and not 100% tested.
8.
t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C192
Document #: 38-05047 Rev. **
Page 5 of 10
Switching Waveforms
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = V
IL
.
12. Address valid prior to or coincident with CE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
C1916
Read Cycle No. 1
[10, 11]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZCE
t
PD
CE
HIGH
V
CC
SUPPLY
CURRENT
C1917
Read Cycle No. 2
[10, 12]
t
WC
DATA VALID
DATA UNDEFINED
HIGH IMPEDANCE
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
HZWE
t
LZWE
t
SD
CE
WE
DATA IN
DATA OUT
ADDRESS
C1918
Write Cycle No. 1 (WE Controlled)
[9]
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