64K x 4 Static RAM
CY7C194
CY7C195
CY7C196
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05162 Rev. **
Revised September 18, 2001
96
Features
High speed
-- 12 ns
Output enable (OE) feature (7C195 and 7C196)
CMOS for optimum speed/power
Low active power
-- 880 mW
Low standby power
-- 220 mW
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C194, CY7C195, and CY7C196 are high-perfor-
mance CMOS static RAMs organized as 65,536 by 4 bits.
Easy memory expansion is provided by active LOW Chip En-
able(s) (CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) and three-state drivers. They have an automatic
power-down feature, reducing the power consumption by 75%
when deselected.
Writing to the device is accomplished when the Chip Enable(s)
(CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) and Write Enable (WE) inputs are both LOW. Data
on the four input pins (I/O
0
through I/O
3
) is written into the
memory location, specified on the address pins (A
0
through
A
15
).
Reading the device is accomplished by taking the Chip En-
able(s) (CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) LOW, while Write Enable (WE) remains HIGH. Un-
der these conditions the contents of the memory location
specified on the address pins will appear on the four data I/O
pins.
A die coat is used to ensure alpha immunity.
CE
Logic Block Diagram
Pin Configurations
1024 x 64 x 4
ARRAY
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
11
A
13
A
12
A
14
A
15
COLUMN
DECODER
ROW DE
CODER
SE
N
S
E A
M
P
S
POWER
DOWN
WE
(OE)
(7C195 and
7C196 ONLY)
I/O
3
CE
2
(7C196 only)
I/O
2
I/O
1
I/O
0
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
7C194
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
3
I/O
2
I/O
1
I/O
0
A
0
GND
12
13
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
7C195
12
13
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
3
I/O
2
I/O
1
I/O
0
A
0
CE
1
A
14
A
15
A
5
A
14
A
15
OE
NC
NC
CE
2
(7C196)
INPUT BUFFER
CE
1
A
9
A
10
7C196
C194-1
C194-2
C194-3
NC
(7C195)
Selection Guide
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
Maximum Access Time (ns)
12
15
20
25
35
45
Maximum Operating Current (mA)
155
145
135
115
115
Maximum Standby Current (mA)
30
30
30
30
30
30
CY7C194
CY7C195
CY7C196
Document #: 38-05162 Rev. **
Page 2 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
]
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial
0
C to +70
C
5V
10%
Electrical Characteristics
Over the Operating Range
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3V
2.2
V
CC
+ 0.3V
V
V
IL
[1]
Input LOW Voltage
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
-
5
+5
-
5
+5
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
-
5
+5
-
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max.,
V
OUT
= GND
-
300
-
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
=Max.,
I
OUT
=0 mA,
f=f
MAX
=1/t
RC
155
145
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
[4]
Max. V
CC
, CE
1,2
> V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
30
30
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
[4]
Max. V
CC
, CE
1,2
> V
CC
- 0.3V,
V
IN
> V
CC
- 0.3V or
V
IN
< 0.3V, f = 0
10
10
mA
Notes:
1.
Minimum voltage is equal to 2.0V for pulse durations of less than 20 ns.
2.
T
A
is the "Instant On" case temperature.
3.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4.
A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
CY7C194
CY7C195
CY7C196
Document #: 38-05162 Rev. **
Page 3 of 12
)
Electrical Characteristics
Over the Operating Range (continued)
7C194-20
7C195-20
7C196-20
7C194-25, 35, 45
7C195-25, 35
7C196-25, 35, 45
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
4.0 mA
2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3V
2.2
V
CC
+0.3V
V
V
IL
Input LOW Voltage
0.5
0.8
0.5
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
5
+5
5
+5
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
5
+5
5
+5
A
I
OS
Output Short
Circuit Current
[3]
V
CC
= Max.,
V
OUT
= GND
300
300
mA
I
CC
V
CC
Operating
Supply Current
V
CC
=Max.,
I
OUT
=0 mA,
f=f
MAX
=1/t
RC
135
115
mA
I
SB1
Automatic CE
Power-Down Current
--TTL Inputs
[4]
Max. V
CC
, CE
1,2
> V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
30
30
mA
I
SB2
Automatic CE
Power-Down Current
--CMOS Inputs
[4]
Max. V
CC
, CE
1,2
> V
CC
0.3V,
V
IN
> V
CC
0.3V or
V
IN
< 0.3V, f = 0
15
15
mA
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
8
pF
C
OUT
Output Capacitance
10
pF
AC Test Loads and Waveforms
[6]
Notes:
5.
Tested initially and after any design or process changes that may affect these parameters.
6.
t
r
= < 3 ns for the -12 and -15 speeds. T.
r
= < 5 ns for the -20 and slower speeds.
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< t
r
< t
r
5V
OUTPUT
R1 481
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
TH
EVENIN EQUIVALENT
ALL INPUT PULSES
C194-4
C194-5
167
CY7C194
CY7C195
CY7C196
Document #: 38-05162 Rev. **
Page 4 of 12
:
Switching Characteristics
Over the Operating Range
[7]
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
12
15
20
25
35
45
ns
t
AA
Address to Data
Valid
12
15
20
25
35
45
ns
t
OHA
Output Hold from
Address Change
3
3
3
3
3
3
ns
t
ACE1
,
t
ACE2
CE LOW to
Data Valid
12
15
20
25
35
45
ns
t
DOE
OE LOW to
Data Valid
7C195,
7C196
5
7
9
10
16
16
ns
t
LZOE
OE LOW to
Low Z
7C195,
7C196
0
0
0
3
3
3
ns
t
HZOE
OE HIGH to
High Z
[8]
7C195,
7C196
5
7
9
11
15
15
ns
t
LZCE1
,
t
LZCE2
CE LOW to
Low Z
[8]
3
3
3
3
3
3
ns
t
HZCE1
,
t
HZCE2
CE HIGH to
High Z
[8,8]
5
7
9
11
15
15
ns
t
PU
CE LOW to
Power-Up
0
0
0
0
0
0
ns
t
PD
CE HIGH to
Power-Down
12
15
20
25
35
45
ns
WRITE CYCLE
[10]
t
WC
Write Cycle Time
12
15
20
25
35
45
ns
t
SCE
CE LOW to Write End
9
10
15
18
22
22
ns
t
AW
Address Set-Up to
Write End
9
10
15
20
25
35
ns
t
HA
Address Hold from
Write End
0
0
0
0
0
0
ns
t
SA
Address Set-Up to
Write Start
0
0
0
0
0
0
ns
t
PWE
WE Pulse Width
8
9
15
18
22
22
ns
t
SD
Data Set-Up to
Write End
8
9
10
10
15
15
ns
t
HD
Data Hold from
Write End
0
0
0
0
0
0
ns
t
LZWE
WE HIGH to
Low Z
[8]
3
3
3
3
3
3
ns
t
HZWE
WE LOW to
High Z
[8, 9]
7
7
10
0
13
0
15
0
20
ns
Notes:
7.
Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
9.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C194
CY7C195
CY7C196
Document #: 38-05162 Rev. **
Page 5 of 12
Switching Waveforms
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected: CE
1
= V
IL
, CE
2
= V
IL
(7C196), and OE = V
IL
(7C195 and 7C196).
13. Address valid prior to or coincident with CE
1
and CE
2
transition LOW.
14. Data I/O will be high impedance if OE = V
IH
(7C195 and 7C196).
15. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Read Cycle No. 1
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
C194-8
[11, 12]
[11, 13]
Read Cycle No. 2
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
C194-6
ICC
ISB
IMPEDANCE
CE
1
, CE
2
OE
(7C195 and
7C196)
DATA OUT
V
CC
SUPPLY
CURRENT
C194-7
Write Cycle No. 1 (CE Controlled)
t
WC
DATA VALID
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
[10, 14, 15]
WE
DATA I/O
ADDRESS
CE
1
CE
2
(7C196)
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