CY7C68015A

PRELIMINARY

CY7C68013A

Document #: 38-08032 Rev. *E

Page 2 of 63

TABLE OF CONTENTS

1.0 EZ-USB FX2LP FEATURES ............................................................................................................6
2.0 APPLICATIONS ...............................................................................................................................7
3.0 FUNCTIONAL OVERVIEW ..............................................................................................................8

3.1 USB Signaling Speed .................................................................................................................8
3.2 8051 Microprocessor ..................................................................................................................8

3.2.1 8051 Clock Frequency ...................................................................................................................... 8
3.2.2 USARTS ............................................................................................................................................ 8
3.2.3 Special Function Registers ............................................................................................................... 8

3.3 I

C Bus ........................................................................................................................................8

3.4 Buses ..........................................................................................................................................9
3.5 USB Boot Methods .....................................................................................................................9
3.6 ReNumerationTM .........................................................................................................................9
3.7 Bus-powered Applications ..........................................................................................................9
3.8 Interrupt System ........................................................................................................................10

3.8.1 INT2 Interrupt Request and Enable Registers ................................................................................10
3.8.2 USB-Interrupt Autovectors ..............................................................................................................10
3.8.3 FIFO/GPIF Interrupt (INT4) .............................................................................................................11

3.9 Reset and Wakeup ...................................................................................................................11

3.9.1 Reset Pin .........................................................................................................................................11
3.9.2 Wakeup Pins ...................................................................................................................................12

3.10 Program/Data RAM .................................................................................................................12

3.10.1 Size ...............................................................................................................................................12
3.10.2 Internal Code Memory, EA = 0 ......................................................................................................12
3.10.3 External Code Memory, EA = 1 ....................................................................................................12

3.11 Register Addresses .................................................................................................................14
3.12 Endpoint RAM .........................................................................................................................15

3.12.1 Size ...............................................................................................................................................15
3.12.2 Organization ..................................................................................................................................15
3.12.3 Setup Data Buffer ..........................................................................................................................15
3.12.4 Endpoint Configurations (High-speed Mode) ................................................................................15
3.12.5 Default Full-Speed Alternate Settings ...........................................................................................16
3.12.6 Default High-Speed Alternate Settings .........................................................................................16

3.13 External FIFO Interface ...........................................................................................................16

3.13.1 Architecture ...................................................................................................................................16
3.13.2 Master/Slave Control Signals ........................................................................................................16
3.13.3 GPIF and FIFO Clock Rates .........................................................................................................17

3.14 GPIF ........................................................................................................................................17

3.14.1 Six Control OUT Signals ...............................................................................................................17
3.14.2 Six Ready IN Signals ....................................................................................................................17
3.14.3 Nine GPIF Address OUT Signals ..................................................................................................17
3.14.4 Long Transfer Mode ......................................................................................................................17

3.15 ECC Generation ......................................................................................................................17

3.15.1 ECC Implementation .....................................................................................................................17

3.16 USB Uploads and Downloads .................................................................................................18
3.17 Autopointer Access .................................................................................................................18
3.18 I

C Controller ..........................................................................................................................18

3.18.1 I

C Port Pins .................................................................................................................................18

3.18.2 I

C Interface Boot Load Access ....................................................................................................18

3.18.3 I

C Interface General Purpose Access .........................................................................................18

CY7C68015A

PRELIMINARY

CY7C68013A

Document #: 38-08032 Rev. *E

Page 3 of 63

TABLE OF CONTENTS

(continued)

3.19 Compatible with Previous Generation EZ-USB FX2 ...............................................................19
3.20 CY7C68013A and CY7C68015A Differences .........................................................................19

4.0 PIN ASSIGNMENTS ......................................................................................................................20

4.1 CY7C68013A/15A Pin Descriptions ..........................................................................................26

5.0 REGISTER SUMMARY ..................................................................................................................34
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................41
7.0 OPERATING CONDITIONS ...........................................................................................................41
8.0 DC CHARACTERISTICS ...............................................................................................................41

8.1 USB Transceiver .......................................................................................................................41

9.0 AC ELECTRICAL CHARACTERISTICS .......................................................................................42

9.1 USB Transceiver .......................................................................................................................42
9.2 Program Memory Read .............................................................................................................42
9.3 Data Memory Read ...................................................................................................................43
9.4 Data Memory Write ...................................................................................................................44
9.5 GPIF Synchronous Signals .......................................................................................................45
9.6 Slave FIFO Synchronous Read ................................................................................................46
9.7 Slave FIFO Asynchronous Read ..............................................................................................47
9.8 Slave FIFO Synchronous Write ................................................................................................48
9.9 Slave FIFO Asynchronous Write ...............................................................................................49
9.10 Slave FIFO Synchronous Packet End Strobe .........................................................................49
9.11 Slave FIFO Asynchronous Packet End Strobe .......................................................................50
9.12 Slave FIFO Output Enable ......................................................................................................50
9.13 Slave FIFO Address to Flags/Data .........................................................................................50
9.14 Slave FIFO Synchronous Address ..........................................................................................51
9.15 Slave FIFO Asynchronous Address ........................................................................................51
9.16 Sequence Diagram .................................................................................................................52

9.16.1 Single and Burst Synchronous Read Example ...........................................................................52
9.16.2 Single and Burst Synchronous Write ............................................................................................53
9.16.3 Sequence Diagram of a Single and Burst Asynchronous Read ....................................................54
9.16.4 Sequence Diagram of a Single and Burst Asynchronous Write ....................................................55

10.0 ORDERING INFORMATION ........................................................................................................56
11.0 PACKAGE DIAGRAMS ...............................................................................................................57
12.0 PCB LAYOUT RECOMMENDATIONS ........................................................................................60
13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES ................................61

CY7C68015A

PRELIMINARY

CY7C68013A

Document #: 38-08032 Rev. *E

Page 4 of 63

LIST OF FIGURES

Figure 1-1. Block Diagram ....................................................................................................................... 6
Figure 3-1. Crystal Configuration............................................................................................................. 8
Figure 3-2. Reset Timing Plots .............................................................................................................. 12
Figure 3-3. Internal Code Memory, EA = 0 ............................................................................................ 13
Figure 3-4. External Code Memory, EA = 1........................................................................................... 14
Figure 3-5. Endpoint Configuration........................................................................................................ 15
Figure 4-1. Signals................................................................................................................................. 21
Figure 4-2. CY7C68013A 128-pin TQFP Pin Assignment..................................................................... 22
Figure 4-3. CY7C68013A 100-pin TQFP Pin Assignment..................................................................... 23
Figure 4-4. CY7C68013A/15A 56-pin SSOP Pin Assignment ............................................................... 24
Figure 4-5. CY7C68013A/15A 56-pin QFN Pin Assignment ................................................................. 25
Figure 9-1. Program Memory Read Timing Diagram............................................................................. 42
Figure 9-2. Data Memory Read Timing Diagram................................................................................... 43
Figure 9-3. Data Memory Write Timing Diagram ................................................................................... 44
Figure 9-4. GPIF Synchronous Signals Timing Diagram....................................................................... 45
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram ................................................................ 46
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram .............................................................. 47
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram ................................................................ 48
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram............................................................... 49
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram........................................... 49
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram ....................................... 50
Figure 9-11. Slave FIFO Output Enable Timing Diagram...................................................................... 50
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram ......................................................... 50
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram.......................................................... 51
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram........................................................ 51
Figure 9-15. Slave FIFO Synchronous Read Sequence and Timing Diagram ...................................... 52
Figure 9-16. Slave FIFO Synchronous Sequence of Events Diagram .................................................. 52
Figure 9-17. Slave FIFO Synchronous Write Sequence and Timing Diagram ...................................... 53
Figure 9-18. Slave FIFO Asynchronous Read Sequence and Timing Diagram .................................... 54
Figure 9-19. Slave FIFO Asynchronous Read Sequence of Events Diagram ....................................... 54
Figure 9-20. Slave FIFO Asynchronous Write Sequence and Timing Diagram .................................... 55
Figure 11-1. 56-lead Shrunk Small Outline Package O56..................................................................... 57
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 8 mm) LF56............................................. 57
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101.......................................... 58
Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128....................................... 59
Figure 13-1. Cross-section of the Area Underneath the QFN Package ................................................ 61
Figure 13-2. Plot of the Solder Mask (White Area) ................................................................................ 61
Figure 13-3. X-ray Image of the Assembly ............................................................................................ 61

CY7C68015A

PRELIMINARY

CY7C68013A

Document #: 38-08032 Rev. *E

Page 5 of 63

LIST OF TABLES

Table 3-1. Special Function Registers ....................................................................................................9
Table 3-2. Default ID Values for FX2LP .................................................................................................9
Table 3-3. INT2 USB Interrupts ............................................................................................................10
Table 3-4. Individual FIFO/GPIF Interrupt Sources ..............................................................................11
Table 3-5. Reset Timing Values ...........................................................................................................12
Table 3-6. Default Full-Speed Alternate Settings .................................................................................16
Table 3-7. Default High-Speed Alternate Settings.................................................................................16
Table 3-8. Strap Boot EEPROM Address Lines to These Values ........................................................18
Table 3-9. Part Number Conversion Table ...........................................................................................19
Table 3-10. CY7C68013A and CY7C68015A pin differences ..............................................................19
Table 4-1. FX2LP Pin Descriptions .......................................................................................................26
Table 5-1. FX2LP Register Summary ...................................................................................................34
Table 8-1. DC Characteristics ...............................................................................................................41
Table 9-1. Program Memory Read Parameters ....................................................................................42
Table 9-2. Data Memory Read Parameters ..........................................................................................43
Table 9-3. Data Memory Write Parameters ..........................................................................................44
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK ..............................45
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK .............................45
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK........................46
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK ......................46
Table 9-8. Slave FIFO Asynchronous Read Parameters ......................................................................47
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK .......................48
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK.....................48
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ...................49
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK 49
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK49
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters ...............................................50
Table 9-15. Slave FIFO Output Enable Parameters .............................................................................50
Table 9-16. Slave FIFO Address to Flags/Data Parameters ................................................................50
Table 9-17. Slave FIFO Synchronous Address Parameters .................................................................51
Table 9-18. Slave FIFO Asynchronous Address Parameters ...............................................................51
Table 10-1. Ordering Information ..........................................................................................................56

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