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Электронный компонент: CY8C22213-24PI

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CY8C22113, CY8C22213
PSoCTM Mixed Signal Array
Preliminary Data Sheet
For Silicon Revision A
December 22, 2003
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone: 800.669.0557
FAX: 425.787.4641
http://www.cypress.com
Document No. 38-12009 Rev. *D
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2
Document No. 38-12009 Rev. *D
December 22, 2003
CY8C22xxx Preliminary Data Sheet
Cypress MicroSystems, Inc. 2003. All rights reserved. PSoCTM (Programmable System-on-ChipTM) is a trademark of
Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective
corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any
license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in
life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress MicroSystems' products in life-support system applications implies that the manufacturer assumes all
risk of such use and in doing so, indemnifies Cypress MicroSystems against all charges.
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December 22, 2003
Document No. 38-12009 Rev. *D
3
Contents
SECTION A OVERVIEW
13
Features ...........................................................................................................................................13
Getting Started .................................................................................................................................14
Development Kits ................................................................................................................14
Tele-Training .......................................................................................................................14
Consultants .........................................................................................................................14
Technical Support ...............................................................................................................14
Application Notes ................................................................................................................14
Top-Level Architecture .....................................................................................................................15
Development Tools ..........................................................................................................................16
PSoC Designer Software Subsystems ................................................................................16
Hardware Tools ...................................................................................................................17
User Modules and Development Process ........................................................................................17
Ordering Information ........................................................................................................................19
Organization and Conventions .........................................................................................................20
Document Organization ......................................................................................................20
Document Conventions .......................................................................................................20
1. Pin
Information ....................................................................................................... 23
1.1
Pin Summary .......................................................................................................................23
1.2
Pinouts .................................................................................................................................24
2. Packaging
Information ............................................................................................ 27
2.1
Packaging Dimensions.........................................................................................................27
2.2
Thermal Impedances ..........................................................................................................30
SECTION B CORE ARCHITECTURE
31
Top-Level Core Architecture ............................................................................................................31
Core Register Summary ...................................................................................................................32
3. CPU Core (M8C) .................................................................................................... 35
3.1
Internal Registers .................................................................................................................35
3.2
Address Spaces ...................................................................................................................35
3.3
Instruction Set Summary......................................................................................................37
3.4
Instruction Format ................................................................................................................38
3.4.1
One-Byte Instructions.....................................................................................38
3.4.2
Two-Byte Instructions.....................................................................................38
3.4.3
Three-Byte Instructions ..................................................................................39
3.5
Addressing Modes ...............................................................................................................39
3.5.1
Source Immediate ..........................................................................................39
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Contents
CY8C22xxx Preliminary Data Sheet
4
Document No. 38-12009 Rev. *D
December 22, 2003
3.5.2
Source Direct ................................................................................................. 40
3.5.3
Source Indexed.............................................................................................. 40
3.5.4
Destination Direct........................................................................................... 40
3.5.5
Destination Indexed ....................................................................................... 41
3.5.6
Destination Direct Source Immediate ............................................................ 41
3.5.7
Destination Indexed Source Immediate ......................................................... 41
3.5.8
Destination Direct Source Direct.................................................................... 42
3.5.9
Source Indirect Post Increment...................................................................... 42
3.5.10
Destination Indirect Post Increment ...............................................................42
3.6
Register Definitions.............................................................................................................. 43
3.6.1
CPU_F (Flag) Register ..................................................................................43
4. Supervisory ROM (SROM) ...................................................................................... 45
4.1
Architectural Description ......................................................................................................45
4.1.1
Additional SROM Feature .............................................................................. 46
4.1.2
SROM Function Descriptions......................................................................... 46
4.2
Register Definitions.............................................................................................................. 49
4.2.1
CPU_SCR1 Register ..................................................................................... 49
4.3
Clocking ............................................................................................................................... 49
5. Interrupt
Controller ................................................................................................. 51
5.1
Architectural Description ......................................................................................................52
5.2
Register Definitions.............................................................................................................. 53
5.2.1
INT_CLRx Register........................................................................................ 53
5.2.2
INT_MSKx Register ....................................................................................... 53
5.2.3
INT_VC Register............................................................................................ 53
5.2.4
CPU_F Register............................................................................................. 53
6. General Purpose IO (GPIO) .................................................................................... 55
6.1
Architectural Description ......................................................................................................55
6.1.1
Digital IO ........................................................................................................ 55
6.1.2
Global IO........................................................................................................ 55
6.1.3
Analog IO ....................................................................................................... 56
6.1.4
GPIO Block Interrupts .................................................................................... 56
6.2
Register Definitions.............................................................................................................. 58
6.2.1
PRTxDR Registers.........................................................................................58
6.2.2
PRTxIE Registers .......................................................................................... 58
6.2.3
PRTxGS Registers.........................................................................................58
6.2.4
PRTxDMx Registers ...................................................................................... 58
6.2.5
PRTxICx Registers ........................................................................................ 59
7. Analog Output Drivers ............................................................................................ 61
7.1
Architectural Description ......................................................................................................61
7.2
Register Definitions.............................................................................................................. 61
7.2.1
ABF_CR0 Register ........................................................................................ 61
8. Internal Main Oscillator (IMO) ................................................................................. 63
8.1
Architectural Description ......................................................................................................63
8.2
Register Definitions.............................................................................................................. 63
8.2.1
IMO_TR Register ........................................................................................... 63
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December 22, 2003
Document No. 38-12009 Rev. *D
5
CY8C22xxx Preliminary Data Sheet
Contents
9. Internal Low Speed Oscillator (ILO) ........................................................................65
9.1
Architectural Description ......................................................................................................65
9.2
Register Definitions ..............................................................................................................65
9.2.1
ILO_TR Register ............................................................................................65
10. 32 kHz Crystal Oscillator (ECO) ..............................................................................67
10.1
Architectural Description ......................................................................................................67
10.1.1
ECO External Components............................................................................68
10.2
Register Definitions ..............................................................................................................68
10.2.1
OSC_CR0 Register........................................................................................68
10.2.2
ECO_TR Register ..........................................................................................69
10.2.3
CPU_SCR1 Register......................................................................................69
11. Phase Locked Loop (PLL) ....................................................................................... 71
11.1
Architectural Description ......................................................................................................71
11.2
Register Definitions ..............................................................................................................71
11.2.1
OSC_CR0 Register........................................................................................71
11.2.2
OSC_CR2 Register........................................................................................72
12. Sleep and Watchdog .............................................................................................. 73
12.1
Architectural Description ......................................................................................................73
12.1.1
32 kHz Clock Selection ..................................................................................73
12.1.2
Sleep Timer ....................................................................................................74
12.1.3
Sleep Bit.........................................................................................................74
12.2
Application Description.........................................................................................................74
12.3
Register Definitions ..............................................................................................................75
12.3.1
INT_MSK0 Register .......................................................................................75
12.3.2
RES_WDT Register .......................................................................................75
12.3.3
OSC_CR0 Register........................................................................................75
12.3.4
CPU_SCR1 Register......................................................................................76
12.3.5
ILO_TR Register ............................................................................................76
12.3.6
ECO_TR Register ..........................................................................................76
12.3.7
CPU_SCR0 Register......................................................................................76
12.4
Timing Diagrams ..................................................................................................................77
12.4.1
Sleep Sequence.............................................................................................77
12.4.2
Wake Up Sequence .......................................................................................78
12.4.3
Bandgap Refresh ...........................................................................................79
12.4.4
Watchdog Timer (WDT) .................................................................................79
12.5
Power Consumption .............................................................................................................80
SECTION C REGISTER REFERENCE
81
Register Conventions .......................................................................................................................81
Register Mapping Tables .................................................................................................................81
Register Map 0 Table: User Space ..............................................................................82
Register Map 1 Table: Configuration Space ................................................................83
13. Register Details ...................................................................................................... 85
13.1
Bank 0 Registers..................................................................................................................86
13.1.1
PRTxDR ........................................................................................................86
13.1.2
PRTxIE ..........................................................................................................87
13.1.3
PRTxGS ........................................................................................................88

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