ADVANCE INFORMATION
18-Mb Pipelined MCM with QDR
TM
Architecture
CYM52KQT36AV25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05041 Rev. **
Revised August 15, 2001
Features
Separate Independent Read and Write Data Ports
-- Supports concurrent transactions
167 MHz Clock for High Bandwidth
-- 2.5 ns Clock-to-Valid access time
Double Data Rate (DDR) interfaces on both Read &
Write Ports (data transferred at 333 MHz) @167 MHz
Two input clocks (K and K) for precise DDR timing
-- SRAM uses rising edges only
Two output clocks (C and C) account for clock skew and
flight time mismatches
Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
13x15 mm, 1.0-mm pitch fBGA package, 165 ball (11x15
matrix)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V1.9V)
JTAG Interface
Variable Impedance HSTL
Functional Description
The CYM52KQT36AV25 is a 2.5V 18M Synchronous Pipe-
lined SRAM equipped with QDR architecture. QDR architec-
ture consists of two separate ports to access the memory ar-
ray. The Read port has dedicated Data Outputs to support
Read operations and the Write Port has dedicated Data inputs
to support Write operations. Access to each port is accom-
plished through a common
address bus. The Read address is
latched on the rising edge of the K clock and the Write address
is latched on the rising edge of K clock. QDR has separate
data inputs and data outputs to completely eliminate the need
to "turn-around" the data bus required with common I/O devic-
es. Accesses to the CYM52KQT36AV25 Read and Write ports
are completely independent of one another. All accesses are
initiated synchronously on the rising edge of the positive input
clock (K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) AND out of the
device on every rising edge of the output clock (C and C) there-
by maximizing performance while simplifying system design.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate inde-
pendently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
A
(17:0)
K
K
D
[35:0]
WPS
BWS
0
Vref
18
BWS
1
18
18
36
D
[17:0]
D
[17:0]
A
(17:0)
C
C
BWS
2
BWS
3
K
K
C
C
K
K
C
C
A
(17:0)
RPS
Q
[35:0]
Q
[17:0]
Q
[17:0]
RPS
RPS
Q
[8:0]
Q
[17:9]
Q
[25:18]
Q
[35:26]
D
[8:0]
D
[17:9]
D
[25:18]
D
[35:26]
TDO
TMS
TCLK
TDI
TDO
TMS
TCLK
TDI
TCLK
TMS
TDI
TDO
CYM52KQT36AV25
ADVANCE INFORMATION
Document #: 38-05041 Rev. **
Page 2 of 25
Selection Guide
CYM52KQT36AV25
-167
CYM52KQT36AV25
-133
CYM52KQT36AV25
-100
Maximum Operating Frequency (MHz)
167
133
100
Maximum Operating Current (mA)
TBD
TBD
TBD
Pin Configuration -
CYM52KQT36AV25
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
VSS
NC
WPS
BWS
2
K
BWS
1
RPS
NC
VSS
NC
B
Q27
Q18
D18
A
BWS
3
K
BWS
0
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
A
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CYM52KQT36AV25
ADVANCE INFORMATION
Document #: 38-05041 Rev. **
Page 3 of 25
Pin Definitions
Name
I/O
Description
D
[35:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
active, a write operation is initiated. Deasserting will deselect the Write port. Deselecting
the Write port will cause D
[35:0]
to be ignored.
BWS
0
, BWS
1,
BWS
2
, BWS
3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 -- active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27]
. BWS
0
, BWS
1
, BWS
2
and BWS
3
are sampled on the same edge as D
[35:0]
.
Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored
and not written into the device.
A
(17:0)
Input-
Synchronous
Address inputs. Sampled on the rising edge of both the K and K clocks during active
read and write operations. These address inputs are multiplexed for both Read and
Write operations. The Read address is latched on the rising edge of the positive input
clock (K) and the Write address is latched on the rising edge of the negative input clock
(K). Internally, the device is organized 256K x 72. Therefore, only 18 address inputs are
needed to access the entire memory array.These inputs are ignored when the appro-
priate port is deselected. Therefore, on the rising edge of the positive input clock (K),
these inputs are ignored if the Read port is deselected. These inputs are ignored on the
rising edge of the negative input clock (K) when the Write port is deselected.
Q
[35:0]
Outputs
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations. When the Read port is deslected, Q
[35:0]
are automatically three-stated.
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the C clock. The
device is organized internally as 256K x 72. Each read access consists of a burst of two
sequential 36-bit transfers.
C
Input-Clock
Positive Output Clock, input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
Input-Clock
Negative Output Clock, input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock, input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[35:0]
when in single clock mode. All ac-
cesses are initiated on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
[35:0]
when in single clock mode.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. Q
[35:0]
output impedance are set to 0.2 x RQ, where RQ
is a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to V
DD
, which enables the minimum impedance mode. This pin cannot be con-
nected directly to GND or left unconnected.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
Not Connect Pins. These are not connected to the die.
CYM52KQT36AV25
ADVANCE INFORMATION
Document #: 38-05041 Rev. **
Page 4 of 25
Introduction
Functional Overview
The CYM52KQT36AV25 is a synchronous pipelined Burst
SRAM equipped with both a Read Port and a Write Port. The
Read port is dedicated to Read operations and the Write Port
is dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read Port. The
CYM52KQT36AV25 multiplexes the address inputs in order to
minimize the number of address pins required. The
CYM52KQT36AV25 latches the Read address on the rising
edge of the positive input clock (K) and latches the Write ad-
dress on the rising edge of the negative input clock (K). By
having separate Read and Write ports, the
CYM52KQT36AV25 completely eliminates the need to "turn
around" the data bus and avoids any possible data contention,
thereby simplifying system design.
Accesses for both ports are initiated by the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K) and all output timing is
referenced to the output clocks (C and C) or K and K when in
single clock mode.
All synchronous data inputs (D
[35:0]
) pass through input regis-
ters controlled by the input clocks (K and K). All synchronous
data outputs (Q
[35:0]
) pass through output registers controlled
by the rising edge of the output clocks (C and C)
All synchronous control inputs (RPS, WPS, BWS
0
, BWS
1
,
BWS
2
, BWS
3
) pass through input registers controlled by the
rising edge of the input clocks (K and K).
Read Operations
Read operations are initiated by asserting RPS active at the
rising edge of the positive input clock (K). The address pre-
sented to A
[17:0]
is stored in the Read address register. Be-
cause the CYM52KQT36AV25 is a 72-bit memory, it will ac-
cess two 36-bit data words with each read operation. Following
the next K clock rise the data is available to be latched out of
the device, triggered by the C clock. On the following C clock
rise the corresponding lower order word of data is driven onto
Q
[36:0]
. On the subsequent rising edge of C the higher order
data word is driven onto Q
[35:0]
. The requested data will be
valid 2.5 ns from the rising edge of the output clock (C or C,
167 MHz device). With the separate Input and Output ports
and the internal logic determining when the device should
drive the data bus, the QDR architecture has eliminated the
need for an output enable input to control the state of the out-
put drivers.
Read accesses can be initiated on every rising edge of the
positive input clock (K). Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C). The CYM52KQT36AV25
will deliver the most recent data for the address location being
accessed. This includes forwarding data when a Read and
Write transactions to the same address location are initiated
on the same clock rise.
When the read port is deselected, the CYM52KQT36AV25 will
first complete the pending read transactions. Synchronous in-
ternal circuitry will automatically three-state the outputs follow-
ing the next rising edge of the positive output clock (C). This
will allow for a seamless transition between devices without the
insertion of wait states.
The CYM52KQT36AV25 is equipped with internal logic that
synchronously controls the state of the output drivers. The log-
ic inside the device determines when the output drivers need
to be active or inactive. This advanced logic eliminates the
need for an asynchronous output enable since the device will
automatically enable/disable the output drivers during the
proper cycles. The CYM52KQT36AV25 will automatically
power-up in a deselcted state with the outputs in a three state
condition.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same clock
rise (K) the data presented to D
[35:0]
is stored into the lower
36-bit Write Data register provided BWS
[3:0]
are all asserted
active. On the subsequent rising edge of the negative input
clock (K), the information presented to A
[17:0]
is latched and
stored in the Write Address Register and the information pre-
sented to D
[35:0]
is also stored into the upper 36-bit Write Data
Register provided BWS
[3:0]
are all asserted active. The 72 bits
of data are then written into the memory array at the specified
location.
Write accesses can be initiated on every rising edge of the
positive clock. Doing so will pipeline the data flow such that
36 bits of data can be transferred into the device on every ris-
ing edge of the input clocks (K and K).
Byte Write operations are supported by the
CYM52KQT36AV25. A write operation is initiated by selecting
the write port using WPS. The bytes that are written are deter-
mined by BWS
0
, BWS
1
, BWS
2
and BWS
3
which are sampled
with each set of 36-bit data words. Asserting the appropriate
Byte Write Select input during the data portion of a write will
allow the data being presented to be latched and written into
the device. Deasserting the Byte Write Select input during the
data portion of a write will allow the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify READ/MODIFY/WRITE operations to a Byte Write op-
eration.
When deselected, the write port will ignore all inputs.
V
REF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as A/C measurement points.
V
DD
Power Supply
Power supply inputs to the core of the device. Should be connected to 2.5V power
supply.
V
SS
Ground
Ground for the device. Should be connected to ground of the system.
V
DDQ
Power Supply
Power supply inputs for the outputs of the device. Should be connected to 1.5V power
supply.
Pin Definitions
(continued)
CYM52KQT36AV25
ADVANCE INFORMATION
Document #: 38-05041 Rev. **
Page 5 of 25
Single Clock Mode
The CYM52KQT36AV25 can be used with a single clock
mode. In this mode the device will recognize only the pair of
input clocks (K and K) that control both the input and output
registers. This operation is identical to the operation if the de-
vice had zero skew between the K/K and C/C clocks. All timing
parameters remain the same in this mode. To use this mode
of operation, the user must tie C and C to V
DD
. During pow-
er-up, the device will sense the single clock input and operate
in either single clock or double clock mode. The clock mode
should not be changed during device operation.
Concurrent Transactions
The Read and Write ports on the CYM52KQT36AV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transac-
tion on the other port. Should the Read and Write ports access
the same location on the rising edge of the positive input clock,
the information presented to D
[35:0]
will be forwarded to Q
[35:0]
such that no latency is required to access valid data. Coher-
ency is conducted on cycle boundaries. Once the second word
of data is latched into the device, the write operation is consid-
ered completed. At this point, any access to that address loca-
tion will receive that data until altered by a subsequent Write
operation. Coherency is not maintained for Write operations
initiated in the cycle after a Read.
Depth Expansion
The CYM52KQT36AV25 has a Port Select input for
each port. This allows for easy depth expansion. Both
Port Selects are sampled on the rising edge of the pos-
itive input clock only (K). Each port select input can de-
select the specified port. Deselecting a port will not af-
fect the other port. All pending transactions (Read and
Write) will be completed prior to the device being dese-
lected.
Programmable Impedance
An external resistor, RQ, must be connected between
the ZQ pin on the SRAM and V
SS
to allow the SRAM to
adjust its output driver impedance. The value of RQ
must be 5X the value of the intended line impedance
driven by the SRAM. The allowable range of RQ to guar-
antee impedance matching with a tolerance of 10% is
between 175
and 350
, with V
DDQ
= 1.5V. The output
impedance is adjusted every 1024 cycles to adjust for
drifts in supply voltage and temperature.
Truth Table
[
1,2
]
Operation
Address
used
RPS
WPS
K
Comments
Deselected
-
H
H
L-H
Read Port is deselected. Outputs three-state following next rising edge of
negative input clock (K) if in single clock mode, or C if using C and C as
the output clocks.
Write Port is deselected. All Write Port inputs are ignored during this clock
rise and the subsequent rising edge of the negative input clock (K).
Begin Read
External
L
H
L-H
Read operation initiated. Addresses are stored in the Read Address Reg-
ister. Following the next K clock rise the first (lower order) 36-bit word will
be available to be driven out onto Q
[35:0]
gated by the rising edge of the
output clock C. On the subsequent rising edge of the negative output clock
(C) the second (higher order) 36-bit word is driven out onto Q
[35:0]
.
Begin Write
External
on next
rising
edge of K
H
L
L-H
Write operation initiated. The information presented to D
[35:0]
is stored in
the Write Data Register. On the subsequent rising edge of the negative
input clock (K) the device will latch the addresses presented to A
[17:0]
and
the data presented to D
[35:0]
]. The entire 72 bits of information will then
be written into the memory array. See Write Description table for byte write
information,
Note:
1.
X = Don't Care, H = Logic HIGH, L = Logic LOW.
2.
Device will power-up deselected and the outputs in a three-state condition.
3.
BWS
0
and BWS
1
asserted active LOW during all cycles. For byte write operations, see Write Description Table.
4.
Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
5.
It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
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