PRELIMINARY

18-Mbit (512K x 36/1M x 18) Flow-Through

SRAM with NoBLTM Architecture

CY7C1371D

CY7C1373D

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05556 Rev. *A

Revised November 3, 2004

Features

· No Bus Latency

(NoBL) architecture eliminates

dead cycles between write and read cycles

· Can support up to 133-MHz bus operations with zero

wait states
-- Data is transferred on every clock

· Pin-compatible and functionally equivalent to ZBTTM

devices

· Internally self-timed output buffer control to eliminate

the need to use OE

· Registered inputs for flow-through operation
· Byte Write capability
· 3.3V/2.5V I/O power supply
· Fast clock-to-output times

-- 6.5 ns (for 133-MHz device)
-- 8.5 ns (for 100-MHz device)

· Clock Enable (CEN) pin to enable clock and suspend

operation

· Synchronous self-timed writes
· Asynchronous Output Enable
· Offered in JEDEC-standard lead-free 100 TQFP, 119-ball

BGA and 165-ball fBGA packages

· Three chip enables for simple depth expansion
· Automatic Power-down feature available using ZZ

mode or CE deselect

· JTAG boundary scan for BGA and fBGA packages
· Burst Capability--linear or interleaved burst order
· Low standby power

Functional Description

[1]

The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x

18 Synchronous Flow-through Burst SRAM designed specifi-

cally to support unlimited true back-to-back Read/Write opera-

tions without the insertion of wait states. The CY7C1371D/

CY7C1373D is equipped with the advanced No Bus Latency

(NoBL) logic required to enable consecutive Read/Write

operations with data being transferred on every clock cycle.

This feature dramatically improves the throughput of data

through the SRAM, especially in systems that require frequent

Write-Read transitions.
All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).
Write operations are controlled by the two or four Byte Write

Select (BW

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Selection Guide

133 MHz

100 MHz

Unit

Maximum Access Time

6.5

8.5

Maximum Operating Current

210

175

Maximum CMOS Standby Current

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 5 of 30

Pin Configurations

(continued)

B
C
D
E

G
H

P
R

DDQ

NC
NC

DQP

DDQ

CLK

NC
NC

TDO

TCK

TDI

TMS

NC / 36M

NC / 72M

DDQ

ADV/LD

DQP

MODE

DQP

CEN

A
B
C
D
E

G
H

N
P

DDQ

NC
NC

DDQ

NC / 72M

DDQ

CLK

NC
NC

TDO

TCK

TDI

TMS

DDQ

NC / 36M

ADV/LD

MODE

DQP

CEN

CY7C1373D (1 Mbit x 18)

CY7C1371D (512K x 36)

119-ball BGA (3 Chip Enables with JTAG)

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 6 of 30

Pin Configurations

(continued)

165-ball fBGA (3 Chip enable with JTAG)

CY7C1371D (512K x 36)

A
B
C
D
E

N
P
R

TDO

NC / 288M

DQP

CEN

CE2

MODE

NC / 36M

NC / 72M

DDQ

CLK

DDQ

TCK

TDI

DDQ

TMS

ADV/LD

NC / 144M

DDQ

DQP

DDQ

DQP

DDQ

CY7C1373D (1 Mbit x 18)

A
B
C
D
E

G
H

N
P
R

TDO

NC / 288M

NC
NC
NC

DQP

CEN

CE2

MODE

NC / 36M

NC / 72M

DDQ

CLK

DDQ

TCK

TDI

DDQ

TMS

ADV/LD

NC / 144M

DDQ

DQP

DDQ

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CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 7 of 30

Pin Definitions

Name

I/O

Description

, A

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the

rising edge of the CLK. A

[1:0]

are fed to the two-bit burst counter.

, BW

Input-

Synchronous

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK.

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is

active LOW. This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input. Used to advance the on-chip address counter or load a new

address. When HIGH (and CEN is asserted LOW) the internal burst counter is

advanced. When LOW, a new address can be loaded into the device for an access.

After being deselected, ADV/LD should be driven LOW in order to load a new

address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified

with CEN. CLK is only recognized if CEN is active LOW.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Combined with the

synchronous logic block inside the device to control the direction of the I/O pins.

When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH,

I/O pins are tri-stated, and act as input data pins. OE is masked during the data

portion of a write sequence, during the first clock when emerging from a deselected

state, when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-

nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since

deasserting CEN does not deselect the device, CEN can be used to extend the

previous cycle when required.

Input-

Asynchronous

ZZ "Sleep" Input. This active HIGH input places the device in a non-time critical

"sleep" condition with data integrity preserved. During normal operation, this pin can

be connected to V

or left floating.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by the addresses presented during the previous

clock rise of the read cycle. The direction of the pins is controlled by OE. When OE

is asserted LOW, the pins behave as outputs. When HIGH, DQ

and DQP

[A:D]

are

placed in a tri-state condition.The outputs are automatically tri-stated during the data

portion of a write sequence, during the first clock when emerging from a deselected

state, and when the device is deselected, regardless of the state of OE.

DQP

I/O-

Synchronous

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to

MODE

Input Strap Pin

Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V

or left floating

selects interleaved burst sequence.

Power Supply

Power supply inputs to the core of the device.

DDQ

I/O Power Supply

Power supply for the I/O circuitry.

Ground

Ground for the device.

TDO

JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If

the JTAG feature is not being utilized, this pin should be left unconnected. This pin

is not available on TQFP packages.

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CY7C1371D

CY7C1373D

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Page 8 of 30

Functional Overview

The CY7C1371D/CY7C1373D is a synchronous flow-through

burst SRAM designed specifically to eliminate wait states

during Write-Read transitions. All synchronous inputs pass

through input registers controlled by the rising edge of the

clock. The clock signal is qualified with the Clock Enable input

signal (CEN). If CEN is HIGH, the clock signal is not recog-

nized and all internal states are maintained. All synchronous

operations are qualified with CEN. Maximum access delay

from the clock rise (t

CDV

) is 6.5 ns (133-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW

can be used to

conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.
Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses
A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory array

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 6.5

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output will be tri-stated

immediately.

Burst Read Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Reads without reasserting the address

inputs. ADV/LD must be driven LOW in order to load a new

address into the SRAM, as described in the Single Read

Access section above. The sequence of the burst counter is

determined by the MODE input signal. A LOW input on MODE

selects a linear burst mode, a HIGH selects an interleaved

burst sequence. Both burst counters use A

and A

in the burst

sequence, and will wrap around when incremented suffi-

ciently. A HIGH input on ADV/LD will increment the internal

burst counter regardless of the state of chip enable inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (Read or Write) is maintained throughout

the burst sequence.

Single Write Accesses
Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address bus

is loaded into the Address Register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

DQs and DQP

On the next clock rise the data presented to DQs and DQP

(or a subset for byte write operations, see truth table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.
The data written during the Write operation is controlled by

signals. The CY7C1371D/CY7C1373D provides byte

write capability that is described in the truth table. Asserting

the Write Enable input (WE) with the selected Byte Write

Select input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations. Byte write

capability has been included in order to greatly simplify

Read/Modify/Write sequences, which can be reduced to

simple byte write operations.
Because the CY7C1371D/CY7C1373D is a common I/O

device, data should not be driven into the device while the

outputs are active. The Output Enable (OE) can be deasserted

HIGH before presenting data to the DQs and DQP

inputs.

TDI

JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not being utilized, this pin can be left floating or connected to V

through

a pull up resistor. This pin is not available on TQFP packages.

TMS

JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not being utilized, this pin can be disconnected or connected to V

. This

pin is not available on TQFP packages.

TCK

JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin

must be connected to V

. This pin is not available on TQFP packages.

No Connects. Not internally connected to the die. 36 Mbit, 72 Mbit, 144 Mbit and

288 Mbit are address expansion pins and are not internally connected to the die.

Pin Definitions

(continued)

Name

I/O

Description

PRELIMINARY

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CY7C1373D

Document #: 38-05556 Rev. *A

Page 9 of 30

Doing so will tri-state the output drivers. As a safety

precaution, DQs and DQP

are automatically tri-stated during

the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Write operations without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

the initial address, as described in the Single Write Access

section above. When ADV/LD is driven HIGH on the subse-

quent clock rise, the Chip Enables (CE

, CE

, and CE

) and

WE inputs are ignored and the burst counter is incremented.

The correct BW

inputs must be driven in each cycle of the

burst write, in order to write the correct bytes of data.

Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

, CE

, and CE

, must remain inactive

for the duration of t

ZZREC

after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

DDZZ

Sleep mode standby current

ZZ > V

0.2V

ZZS

Device operation to ZZ

ZZ > V

0.2V

CYC

ZZREC

ZZ recovery time

ZZ < 0.2V

CYC

ZZI

ZZ active to sleep current

This parameter is sampled

CYC

RZZI

ZZ Inactive to exit sleep current

This parameter is sampled

Truth Table

[ 2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used

ZZ ADV/LD WE BW

CEN CLK

Deselect Cycle

None

L->H

Tri-State

Deselect Cycle

None

L->H

Tri-State

Deselect Cycle

None

L->H

Tri-State

Continue Deselect Cycle

None

L->H

Tri-State

Read Cycle (Begin Burst)

External

L->H Data Out (Q)

Read Cycle (Continue Burst)

L->H Data Out (Q)

NOP/Dummy Read (Begin Burst) External

L->H

Tri-State

Dummy Read (Continue Burst)

L->H

Tri-State

Notes:

2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. BW

= 0 signifies at least one Byte Write Select is active, BW

= Valid signifies that the desired byte write

selects are asserted, see truth table for details.

3. Write is defined by BW

, and WE. See truth table for Read/Write.

4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP

pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP

= Tri-state when OE

is inactive or when the device is deselected, and DQs and DQP

= data when OE is active.

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CY7C1373D

Document #: 38-05556 Rev. *A

Page 10 of 30

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1371D/CY7C1373D incorporates a serial boundary

scan test access port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE Standard 1149.1-1900, but

doesn't have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The

TAPoperates using JEDEC-standard 3.3V or 2.5V I/O logic

levels.

The CY7C1371D/CY7C1373D contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V

through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

Note:

9. Table only lists a partial listing of the byte write combinations. Any Combination of BW

is valid Appropriate write will be done based on which byte write is active.

Write Cycle (Begin Burst)

External

L->H Data In (D)

Write Cycle (Continue Burst)

L->H Data In (D)

NOP/Write Abort (Begin Burst)

None

L->H

Tri-State

Write Abort (Continue Burst)

L->H

Tri-State

Ignore Clock Edge (Stall)

Current

L->H

Sleep Mode

None

Tri-State

Truth Table

(continued)

[ 2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used

ZZ ADV/LD WE BW

CEN CLK

Partial Truth Table for Read/Write

[2, 3, 9]

Function (CY7C1371D)

Read

Write No bytes written

Write Byte A (DQ

and DQP

)

Write Byte B (DQ

and DQP

)

Write Byte C (DQ

and DQP

)

Write Byte D (DQ

and DQP

)

Write All Bytes

Partial Truth Table for Read/Write

[2, 3,9]

Function (CY7C1373D)

Read

Write - No bytes written

Write Byte A (DQ

and DQP

)

Write Byte B (DQ

and DQP

)

Write All Bytes

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CY7C1373D

Document #: 38-05556 Rev. *A

Page 11 of 30

TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)
The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see figure. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V

) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.
At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers
Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Instruction Register
Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.
When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary "01" pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register
To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

) when the BYPASS instruction is executed.

Boundary Scan Register
The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register

election

Circuitr

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI

TDO

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CY7C1373D

Document #: 38-05556 Rev. *A

Page 12 of 30

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI and the LSB is connected to TDO.

Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set

Overview
Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.
The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O

buffers. The SRAM does not implement the 1149.1 commands

EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather, it performs a capture of the I/O

ring when these instructions are executed.
Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in this SRAM TAP controller,

and therefore this device is not compliant to 1149.1. The TAP

controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction

instruction has been loaded. There is one difference between

the two instructions. Unlike the SAMPLE/PRELOAD

instruction, EXTEST places the SRAM outputs in a High-Z

state.

IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.
The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t

and t

). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.
Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required--that is, while data

captured is shifted out, the preloaded data can be shifted in.

BYPASS
When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Reserved
These instructions are not implemented but are reserved for

future use. Do not use these instructions.

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 13 of 30

TAP Timing

TAP AC Switching Characteristics

Over the Operating Range

[10, 11]

Parameter

Description

Min.

Max.

Unit

Clock
t

TCYC

TCK Clock Cycle Time

TCK Clock Frequency

MHz

TCK Clock HIGH time

TCK Clock LOW time

Output Times
t

TDOV

TCK Clock LOW to TDO Valid

TDOX

TCK Clock LOW to TDO Invalid

Set-up Times
t

TMSS

TMS Set-up to TCK Clock Rise

TDIS

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

Hold Times
t

TMSH

TMS hold after TCK Clock Rise

TDIH

TDI Hold after Clock Rise

Capture Hold after Clock Rise

Notes:

10. t

and t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

11. Test conditions are specified using the load in TAP AC test Conditions. t

= 1 ns.

Test Clock

(TCK)

Test Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON'T CARE

UNDEFINED

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 14 of 30

3.3V TAP AC Test Conditions

Input pulse levels ............................................... .V

to 3.3V

Input rise and fall times ................................................... 1 ns
Input timing reference levels ...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input pulse levels.................................................V

to 2.5V

Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ .1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V

2.5V TAP AC Output Load Equivalent

Note:

12. All voltages referenced to V

(GND).

TDO

1.5V

20pF

Z = 50

TDO

1.25V

20pF

Z = 50

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; V

= 3.3V ±0.165V unless otherwise noted)

[12]

Parameter

Description

Conditions

Min.

Max.

Unit

OH1

Output HIGH Voltage I

= 4.0 mA

DDQ

= 3.3V

2.4

= 1.0 mA

DDQ

= 2.5V

2.0

OH2

Output HIGH Voltage I

= 100 µA

DDQ

= 3.3V

2.9

DDQ

= 2.5V

2.1

OL1

Output LOW Voltage

= 8.0 mA

DDQ

= 3.3V

0.4

= 1.0 mA

DDQ

= 2.5V

0.4

OL2

Output LOW Voltage

= 100 µA

DDQ

= 3.3V

0.2

DDQ

= 2.5V

0.2

Input HIGH Voltage

DDQ

= 3.3V

2.0

+ 0.3

DDQ

= 2.5V

1.7

+ 0.3

Input LOW Voltage

DDQ

= 3.3V

0.5

0.7

DDQ

= 2.5V

0.3

0.7

Input Load Current

GND < V

< V

DDQ

µA

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 15 of 30

Identification Register Definitions

Instruction Field

CY7C1371D

(512KX36)

CY7C1373D

(1 MbitX18)

Description

Revision Number (31:29)

000

Describes the version number

Device Depth (28:24)

01011

Reserved for internal use

Device Width (23:18)

001001

Defines memory type and architecture

Cypress Device ID (17:12)

100101

010101

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100

Allows unique identification of SRAM vendor

ID Register Presence Indicator (0)

Indicates the presence of an ID register

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x18)

Instruction

Bypass

Boundary Scan Order (119-ball BGA package)

Boundary Scan Order (165-ball fBGA package)

Identification Codes

Instruction

Code

Description

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 20 of 30

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with

Power Applied.............................................55°C to +125°C
Supply Voltage on V

Relative to GND........ 0.5V to +4.6V

DC Voltage Applied to Outputs

in Tri-State........................................... 0.5V to V

DDQ

+ 0.5V

DC Input Voltage....................................0.5V to V

+ 0.5V

Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA

Operating Range

Range

Ambient

Temperature

DDQ

Commercial

0°C to +70°C 3.3V

5%/+10% 2.5V 5%

to V

Industrial

40°C to +85°C

Electrical Characteristics

Over the Operating Range

[16, 17]

Parameter

Description

Test Conditions

Min.

Max.

Unit

Power Supply Voltage

3.135

3.6

DDQ

I/O Supply Voltage

DDQ

= 3.3V

3.135

DDQ

= 2.5V

2.375

2.625

Output HIGH Voltage

DDQ

= 3.3V, V

= Min., I

= 4.0 mA

2.4

DDQ

= 2.5V, V

= Min., I

= 1.0 mA

2.0

Output LOW Voltage

DDQ

= 3.3V, V

= Min., I

= 8.0 mA

0.4

DDQ

= 2.5V, V

= Min., I

= 1.0 mA

0.4

Input HIGH Voltage

[16]

DDQ

= 3.3V

2.0

+ 0.3V

DDQ

= 2.5V

1.7

+ 0.3V

Input LOW Voltage

[16]

DDQ

= 3.3V

0.3

0.8

DDQ

= 2.5V

0.3

0.7

Input Load

GND

DDQ

µA

Input Current of MODE Input = V

µA

Input = V

µA

Input Current of ZZ

Input = V

µA

Input = V

µA

Operating Supply

Current

= Max., I

OUT

= 0 mA,

f = f

MAX

= 1/t

CYC

7.5-ns cycle, 133 MHz

210

10-ns cycle, 100 MHz

175

SB1

Automatic CE

Power-down

Current--TTL Inputs

= Max, Device Deselected,

or V

f = f

MAX

, inputs switching

7.5-ns cycle, 133 MHz

140

10-ns cycle, 100 MHz

120

SB2

Automatic CE

Power-down

Current--CMOS Inputs

= Max, Device Deselected,

0.3V or V

> V

0.3V,

f = 0, inputs static

All speeds

SB3

Automatic CE

Power-down

Current--CMOS Inputs

= Max, Device Deselected, or

0.3V or V

> V

DDQ

0.3V

f = f

MAX

, inputs switching

7.5-ns cycle, 133 MHz

130

10-ns cycle, 100 MHz

110

SB4

Automatic CE

Power-down

Current--TTL Inputs

= Max, Device Deselected,

0.3V or V

0.3V

, f =

0, inputs static

All Speeds

Notes:

16. Overshoot: V

(AC) < V

+1.5V (Pulse width less than t

CYC

/2), undershoot: V

(AC) > 2V (Pulse width less than t

CYC

/2).

17. T

Power-up

: Assumes a linear ramp from 0V to V

(min.) within 200 ms. During this time V

< V

and V

DDQ

< V

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 21 of 30

Note:

18. Tested initially and after any design or process change that may affect these parameters.

Thermal Resistance

[18]

Parameter

Description

Test Conditions

TQFP

Package

BGA

Package

fBGA

Package

Unit

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures for

measuring thermal impedance,

per EIA / JESD51.

°C/W

Thermal Resistance

(Junction to Case)

°C/W

Capacitance

[18]

Parameter

Description

Test Conditions

TQFP

Package

BGA

Package

fBGA

Package

Unit

Input

Capacitance

= 25

°C, f = 1 MHz,

= 3.3V

DDQ

= 2.5V

CLK

Clock Input Capacitance

I/O

Input/Output Capacitance

AC Test Loads and Waveforms

OUTPUT

R = 317

R = 351

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

= 50

= 1.5V

3.3V

ALL INPUT PULSES

DDQ

GND

90%

10%

90%

10%

1ns

(c)

OUTPUT

R = 1667

R = 1538

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

= 50

= 1.25V

2.5V

ALL INPUT PULSES

DDQ

GND

90%

10%

90%

10%

1ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 22 of 30

Switching Characteristics

Over the Operating Range

[23, 24]

Parameter

Description

133 MHz

100 MHz

Unit

Min.

Max.

Min.

Max.

POWER

[19]

Clock
t

CYC

Clock Cycle Time

7.5

Clock HIGH

2.1

2.5

Clock LOW

2.1

2.5

Output Times
t

CDV

Data Output Valid After CLK Rise

6.5

8.5

DOH

Data Output Hold After CLK Rise

2.0

CLZ

Clock to Low-Z

[20, 21, 22]

2.0

CHZ

Clock to High-Z

[20, 21, 22]

4.0

5.0

OEV

OE LOW to Output Valid

3.2

3.8

OELZ

OE LOW to Output Low-Z

[20, 21, 22]

OEHZ

OE HIGH to Output High-Z

[20, 21, 22]

4.0

5.0

Setup Times
t

Address Set-up Before CLK Rise

1.5

ALS

ADV/LD Set-up Before CLK Rise

1.5

WES

WE, BW

Set-up Before CLK Rise

1.5

CENS

CEN Set-up Before CLK Rise

1.5

Data Input Set-up Before CLK Rise

1.5

CES

Chip Enable Set-Up Before CLK Rise

1.5

Hold Times
t

Address Hold After CLK Rise

0.5

ALH

ADV/LD Hold After CLK Rise

0.5

WEH

WE, BW

Hold After CLK Rise

0.5

CENH

CEN Hold After CLK Rise

0.5

Data Input Hold After CLK Rise

0.5

CEH

Chip Enable Hold After CLK Rise

0.5

Notes:

19. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

(minimum) initially, before a read or write operation

can be initiated.

20. t

CHZ

, t

CLZ

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

21. At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

22. This parameter is sampled and not 100% tested.
23. Timing reference level is 1.5V when V

DDQ

= 3.3V and is 1.25V when V

DDQ

= 2.5V.

24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 26 of 30

Ordering Information

Speed

(MHz)

Ordering Code

Package

Name

Part and Package Type

Operating

Range

133

CY7C1371D-133AXC

A101

Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Commercial

CY7C1373D-133AXC
CY7C1371D-133AXI

CY7C1373D-133AXI

A101

Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Industrial

CY7C1371D-133BGC

BG119

119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG

Commercial

CY7C1373D-133BGC
CY7C1371D-133BGI

BG119

119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG

Industrial

CY7C1373D-133BGI
CY7C1371D-133BZC

BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables and JTAG

Commercial

CY7C1373D-133BZC
CY7C1371D-133BZI

BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables and JTAG

Industrial

CY7C1373D-133BZI
CY7C1371D-133BGXC

BG119

Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables

and JTAG

Commercial

CY7C1373D-133BGXC
CY7C1371D-133BGXI

BG119

Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables

and JTAG

Industrial

CY7C1373D-133BGXI
CY7C1371D-133BZXC

BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x

1.4mm)3 Chip Enables and JTAG

Commercial

CY7C1373D-133BZXC
CY7C1371D-133BZXI

BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x

1.4mm)3 Chip Enables and JTAG

Industrial

CY7C1373D-133BZXI

100

CY7C1371D-100AXC

A101

Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Commercial

CY7C1373D-100AXC
CY7C1371D-100AXI

A101

Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Industrial

CY7C1373D-100AXI
CY7C1371D-100BGC

BG119

119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG

Commercial

CY7C1373D-100BGC
CY7C1371D-100BGI

BG119

119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG

Industrial

ICY7C1373D-100BGI
CY7C1371D-100BZC

BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables and JTAG

Commercial

CY7C1373D-100BZC
CY7C1371D-100BZI

BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables and JTAG

Industrial

CY7C1373D-100BZI
CY7C1371D-100BGXC

BG119

Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables

and JTAG

Commercial

CY7C1373D-100BGXC
CY7C1371D-100BGXI

BG119

Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables

and JTAG

Industrial

ICY7C1373D-100BGXI
CY7C1371D-100BZXC

BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x

1.4mm) 3 Chip Enables and JTAG

Commercial

CY7C1373D-100BZXC
CY7C1371D-100BZXI

BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x

1.4mm) 3 Chip Enables and JTAG

Industrial

CY7C1373D-100BZXI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (Ordering Code:

BGX) will be available in 2005.

PRELIMINARY

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *A

Page 29 of 30

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. i486 is a trademark, and Intel and Pentium

are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names

mentioned in this document are the trademarks of their respective holders.

Package Diagrams

(continued)

51-85180-**

165 FBGA 13 x 15 x 1.40 MM BB165D

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ICY7C1373D-100BGXI

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ICY7C1373D-100BGXI