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Электронный компонент: W127A

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PRELIMINARY
Spread Spectrum 3 DIMM System Frequency Synthesizer w/AGP
W127/W127-A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 20, 1999, rev. 09.1
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology
I
2
C interface
Four copies of CPU Output
Six copies of PCI Output
Two copies of AGP Output
One copy of 48-MHz USB Output
One copy of 24-MHz SIO Output
Twelve copies of SDRAM Output
One buffered copy of 14.318-MHz reference input
Mode input pin selects optional power management in-
put control pins (reconfigures pins 29, 30, 31, and 32)
Smooth frequency transition upon frequency
reselection
Available in 48-pin SSOP (300 mils)
Standard W127 device supports up to 112-MHz opera-
tions. High-performance option W127-A supports up to
124-MHz.
Key Specifications
Supply Voltages: .......... V
DDQ3
= 3.3V, V
DDQ2
= 3.3V or 2.5V
CPU Cycle to Cycle Jitter: ........................................... 250 ps
CPU to AGP Skew:..................................................0500 ps
AGP to PCI Skew: .................................. 1.5 ns (AGP Leads)
CPU Output Edge Rate: ............................................ >1 V/ns
SDRAM Output Edge Rate:.................................... >1.5 V/ns
Note: All skews are optimized @V
DDQ2
= V
DDQ3
= 3.3V5%.
Skews are not guaranteed for V
DDQ2
= 2.5V.
.
Notes:
1.
Configuration "110" is supported by W127-A only (see shaded row of Table 1).
2.
Signal names with "*" denote pins have internal 250K pull-up resistor, though not relied upon for pulling to V
DDQ3
. Signal names with parenthesis denote function
is selectable by MODE pin strapping.
Table 1. Pin Selectable Frequency
[1]
Input Address
CPU
(MHz)
AGP
(MHz)
PCI
(MHz)
FS2
FS1
FS0
0
0
0
68.5
68.5
34.25
0
0
1
112
74.6
37.3
0
1
0
95.25
63.5
31.75
0
1
1
100
66.6
33.3
1
0
0
83.3
55.53
27.77
1
0
1
75.0
75
37.5
1
1
0
124
82.6
41.3
1
1
1
66.6
66.6
33.3
Block Diagram
Pin Configuration
[2]
VDDQ3
VDDQ3
REF/SD_SEL*
GND
X1
X2
VDDQ3
PCI_F/FS2*
PCI0
GND
PCI1
PCI2
PCI3
PCI4
GND
GND
AGP_F/MODE*
AGP0
VDDQ3
SDRAM11
SDRAM10
VDDQ3
SDATA
VDDQ3
W
1
27/
W1
27-
A
48MHz/FS1*
24MHz/FS0*
GND
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4(AGP_STOP#)*
SDRAM5(PWR_DWN#)*
SDRAM6(CPU_STOP#)*
SDRAM7(PCI_STOP#)*
GND
SDRAM8
SDRAM9
SCLOCK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ3
SDRAM0:11
AGP_F/MODE
AGP0
XTAL OSC
PLL Ref
1
X2
X1
PCI_F/FS2
(PWR_DWN#)
Power Down
Control
48MHZ/FS1
24MHZ/FS0
PLL2
Serial Port
SCLOCK
SDATA
Device
(CPU_STOP#)
Control
2
1
I/O
I/O
VDDQ3
12
2
I/O
REF/SD_SEL
PLL1
Freq
1.5
CPU0:3
CPU
STOP
PCI0:4
AGP
STOP
(AGP_STOP#)
PCI
STOP
(PCI_STOP#)
SDRAM
STOP
I/O
I/O
/
5
4
VDDQ3
VDDQ2
W127/W127-A
PRELIMINARY
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:3
44, 43,
41, 40
O
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled
by the CPU_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ2.
PCI_F/FS2
8
I/O
Free-running PCI Clock Output and Frequency Selection Bit 2: As an output,
this pin works in conjunction with PCI0:4. Output voltage swing is controlled by
voltage applied to VDDQ3.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per Table 1, "Pin Selectable Frequency" on page 1.
PCI0:4
9, 11, 12, 13,
14
O
PCI Clock Outputs 0 through 4: Output voltage swing is controlled by voltage
applied to VDDQ3. Outputs are held LOW if PCI_STOP# is set LOW.
SDRAM0:3
SDRAM8:11
38, 37, 35, 34,
27, 26, 21, 20
O
SDRAM Clock Outputs: These eight SDRAM clock outputs run synchronous to
the CPU clock outputs or AGP clock output as selected using SD_SEL per Table 2.
SDRAM4:7
32, 31, 30, 29
I/O
SDRAM Clock Outputs: These four SDRAM clock outputs run synchronous to
the CPU clock outputs or AGP clock output as selected using SD_SEL per Table
2
. If programmed as inputs, (refer to MODE pin description), these pins are used
for STOP_ CPU, AGP, PCI, and power-down control.
48MHZ/FS1
48
I/O
48-MHz Output and Frequency Selection Bit 1: Fixed clock output that defaults
to 48 MHz following device power-up.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per Table 1, "Pin Selectable Frequency" on page 1.
24MHZ/FS0
47
I/O
24-MHz Output and Frequency Selection Bit 0: Fixed clock output that defaults
to 24 MHz following device power-up.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:2 determines the power-up default frequency of device output clocks
as per Table 1, "Pin Selectable Frequency" on page 1.
AGP_F/MODE
17
I/O
Free-running AGP Output and Mode Control Input: As an output, this pin works
in conjunction with AGP0 and is a free running clock. When an input, it determines
the functions for pin 29, 30, 31, and 32. See Table 3.
AGP0
18
O
AGP Output: This output is controlled by the AGP_STOP# pin.
REF/SD_SEL
3
I/O
Fixed 14.318-MHz and SDRAM Output Selection: As an output, this pin is used
for various system applications. Output voltage swing is controlled by voltage
applied to VDDQ3.
When an input, this pin selects the SDRAM to run synchronous to either CPU or
AGP. See Table 2.
X1
5
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
6
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
SDATA
23
I
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Inter-
face section that follows.
SCLOCK
25
I
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
VDDQ3
1, 2, 7, 19, 22,
24, 36
P
Power Connection: Connected to 3.3V supply.
VDDQ2
42
P
Power Connection: Power Supply for CPU0:3 clock outputs. (3.3V Supply)
GND
4, 10, 15, 16,
28, 33, 39, 45,
46
G
Ground Connection: Connect all ground pins to the common system ground
plane.
W127/W127-A
PRELIMINARY
3
W127/W127-A Pin Selection Tables
Overview
The W127/W127-A was designed specifically to provide all
clock signals required for a motherboard designed with the Via
MVP3 chipset using either a Pentium or K6 microprocessor.
Although it can be used with split voltages (3.3/2.5), the skew
specifications are guaranteed only for single 3.3V supply. The
primary distinguishing feature of the W127/W127-A is the
95.25-MHz CPU frequency option, which supports the K6 333-
MHz CPU.
Twelve SDRAM outputs are provided for support of up to 3
SDRAM DIMM modules. Unused clock outputs can be dis-
abled through the I
2
C interface to reduce system power con-
sumption and more importantly reduce EMI emissions.
Functional Description
I/O Pin Operation
Pins 3, 8, 17, 47, and 48 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power-
up, the logic state of each pin is latched and the pins then
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
An external 10-k
"strapping" resistor is connected between
each l/O pin and ground or V
DDQ3
. Connection to ground sets
a latch to "0," connection to V
DDQ3
sets a latch to "1." Figure 1
and Figure 2 show two suggested methods for strapping resis-
tor connection.
Upon W127/W127-A power-up, the first 2 ms of operation is
used for input logic selection. During this period, the 24-MHz,
48-MHz, REF, PCI_F and AGP_F clock output buffers are
three-stated, allowing the output strapping resistor on each l/O
pin to pull the pin and its associated capacitive clock load to
either a logic HIGH or logic LOW state. At the end of the 2-ms
period, the established logic 0 or 1 condition of each l/O pin is
latched. Next the output buffers are enabled, converting all l/O
pins into operating clock outputs. The 2-ms timer starts when
V
DDQ3
reaches 2.0V. The input bits can only be reset by turn-
ing V
DDQ3
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 40
(nominal), which is minimally
affected by the 10-k
strap to ground or V
DDQ3
. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DDQ3
should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered, assum-
ing that V
DDQ3
has stabilized. If V
DDQ3
has not yet reached full
value, output frequency initially may be below target but will
increase to target once V
DDQ3
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Table 2. SD_SEL Function
SD_SEL
SDRAM0:11
1
Running @ CPU Frequency
0
Running @ AGP Frequency
Table 3. Mode Function
Pin Function
Mode
Pin 29
Pin 30
Pin 31
Pin 32
1
SDRAM7
SDRAM6
SDRAM5
SDRAM4
0
PCI_STOP#
CPU_STOP#
PWR_DWN#
AGP_STOP#
Table 4. Power Management Pin Function
SIGNAL
=0
=1
CPU_STOP#
CPU0:3 & SDRAM0:11 = LOW
Active
PCI_STOP#
PCI0:4 = LOW
Active
AGP_STOP#
AGP0 = LOW
Active
PWR_DWN#
All Clock Outputs LOW
Active
W127/W127-A
PRELIMINARY
4
CPU/PCI Frequency Selection
CPU output frequency is selected with I/O pins 8, 47, and 48.
Refer to Table 1 for CPU/PCI frequency programming informa-
tion. Alternatively, frequency selections are available through
the serial data interface. Refer to Table 8, "Additional Frequen-
cy Selections through Serial Data Interface Data Bytes," on
page 9.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serially terminated clock
lines. The W127/W127-A outputs are CMOS-type, which pro-
vide rail-to-rail output swing.
Crystal Oscillator
The W127/W127-A requires one input reference clock to syn-
thesize all output frequencies. The reference clock can be ei-
ther an externally generated clock signal or the clock generat-
ed by the internal crystal oscillator. When using an external
clock signal, pin X1 is used as the clock input and pin X2 is left
open. The input threshold voltage of pin X1 is (V
DDQ3
)/2.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W127/W127-A
incorporates the necessary feedback resistor and crystal load
capacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 20 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
20 pF should be used. This will typically yield reference fre-
quency accuracies within 100 ppm. To achieve similar accu-
racies with a crystal calling for a greater load, external capac-
itors must be added such that the total load (internal, external,
and parasitic capacitors) equals that called for by the crystal.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W127/W127-A
V
DDQ3
Clock Load
R
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W127/W127-A
V
DD
Clock Load
R
10 k
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
W127/W127-A
PRELIMINARY
5
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is 0.5% of the center frequen-
cy. Figure 4 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc-
tion. Contact your local Sales representative for details on
these devices.
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate values for bits 10 in data byte 0 of the
I
2
C data stream. Refer to Table 7 for more details.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
Figure 4. Typical Modulation Profile
MAX (+.0.5%)
MIN. (0.5%)
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
FREQUENCY