PRELIMINARY
Spread Spectrum Desktop/Notebook System Clock
W130
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 27, 1999, rev. **
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology
Six copies of CPU Clock
Eight copies of PCI Clock (synchronous w/CPU clock)
Two copies of 14.318-MHz IOAPIC Clock
Two copies of 48-MHz USB Clock
Three buffered copies of 14.318-MHz reference input
Input is a 14.318-MHz XTAL or reference signal
Selectable 100-MHz or 66-MHz CPU Clocks
Power management control input pins
Test mode and output three-state capability
Key Specifications
Supply Voltages: ....................................... V
DDQ3
= 3.3V5%
V
DDQ2
= 2.5V5%
CPU Clock Jitter: ........................................................ 200 ps
CPU0:5 Clock Skew: ...................................................175 ps
PCI_F, PCI1:7 Clock Skew: ......................................... 500 ps
CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads)
Logic inputs have 250-k
pull-up resistors except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66#
SEL1
SEL0
CPU
PCI
SPREAD#=0
0
0
0
HI-Z
HI-Z
Don't Care
0
0
1
66.6
33.3
0.9% Center
0
1
0
66.6
33.3
1% Down
0
1
1
66.6
33.3
0.5% Down
1
0
0
X1/2
X1/6
Don't Care
1
0
1
100
33.3
0.9% Center
1
1
0
100
33.3
1% Down
1
1
1
100
33.3
0.5% Down
Pin Configuration
Block Diagram
VDDQ3
REF0
VDDQ2
APIC0
CPU0
CPU1
CPU3
CPU5
PCI_F
XTAL
PLL Ref Freq
PLL 1
100/66#_SEL
X2
X1
REF1
VDDQ3
Stop
Clock
Control
Stop
Clock
Control
PCI1
PWR_DWN#
Power
Down
Control
PCI2
PCI3
PCI4
PCI5
48MHz
48MHz
PLL2
2/3
OSC
REF2
VDDQ2
PCI_STOP#
CPU_STOP#
PCI6
PCI7
VDDQ3
APIC1
SEL0
SEL1
VDDQ3
SPREAD#
CPU2
CPU4
Power
Down
Control
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
VDDQ3
REF2
VDDQ2
APIC0
APIC1
VDDQ2
CPU0
CPU1
CPU2
CPU3
GND
VDDQ2
CPU4
CPU5
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL0
SEL1
SEL100/66#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W130
PRELIMINARY
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:5
42, 41, 40,
39, 36, 35
O
CPU Clock Outputs 0 through 5: These six CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI1:7
8, 10, 11, 13,
14, 16, 17
O
PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
7
O
Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
CPU_STOP#
30
I
CPU_STOP# Input: When brought LOW, clock outputs CPU0:5 are stopped LOW
after completing a full clock cycle (23 CPU clock latency). When brought HIGH,
clock outputs CPU0:5 start beginning with a full clock cycle (23 CPU clock latency).
PCI_STOP#
31
I
PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle.
SPREAD#
28
I
SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking.
APIC0:1
45, 44
O
I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output volt-
age swing is controlled by VDDQ2.
48MHz
22, 23
O
48-MHz Outputs: Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.
REF0:2
1, 2, 47
O
Fixed 14.318-MHz Outputs 0 through 2: Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
SEL100/66#
SEL1, SEL0
25, 26, 27
I
Frequency Selection Input: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1.
X1
4
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or reference signal.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
PWR_DWN#
29
I
Power Down Control: When this input is LOW, device goes into a low-power con-
dition. All outputs are held LOW while in power-down. CPU and PCI clock outputs
are stopped LOW after completing a full clock cycle (23 CPU clock cycle latency).
When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at
full operating frequency (3 ms maximum latency).
VDDQ3
9, 15, 19, 21,
33, 48
P
Power Connection: Power supply for core logic, PLL circuitry, PCI output buffers,
reference output buffers, and 48-MHz output buffers. Connected to 3.3V supply.
VDDQ2
37,43,46
P
Power Connection: Power supply for APIC0:1and CPU0:5 output buffers. Con-
nected to 2.5V supply.
GND
3, 6, 12, 18,
20, 24, 32,
34, 38
G
Ground Connection: Connect all ground pins to the common system ground
plane.
W130
PRELIMINARY
3
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 1.
As shown in Figure 1, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is 0.5%, 0.9%, or 1.0% of
the selected frequency. Figure 2 details the Cypress spreading
pattern. Cypress does offer options with more spread and
greater EMI reduction. Contact your local Sales representative
for details on these devices.
Spread Spectrum clocking is activated or deactivated by
SPREAD# input (pin 28).
S p rea d
S p e ctru m
E n a b le d
E M I R e d u c tio n
S pre a d
S p e ctru m
Non-
S S FT G
Ty p ic a l C lo c k
F re q u e n c y S p an ( M H z)
-S S %
+ S S %
Am
p
l
i
t
u
d
e
(
d
B)
5 d B /d iv
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+0.5%)
MIN (0.5%)
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
100
%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
100
%
FREQUENCY
Figure 2. Typical Modulation Profile
W130
PRELIMINARY
4
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
ESD
PROT
Input ESD Protection
2 (min.)
kV
DC Electrical Characteristics:
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
I
DDQ3
3.3V Supply Current
CPU0:5 = 100 MHz
Outputs Loaded
[1]
95
mA
I
DDQ2
2.5V Supply Current
CPU0:5 = 100 MHz
Outputs Loaded
[1]
75
mA
Logic Inputs
V
IL
Input Low Voltage
GND 0.3
0.8
V
V
IH
Input High Voltage
2.0
V
DD
+ 0.3
V
I
IL
Input Low Current
[2]
25
A
I
IH
Input High Current
[2]
10
A
I
IL
Input Low Current (SEL100/66#)
5
A
I
IH
Input High Current (SEL100/66#)
5
A
Clock Outputs
V
OL
Output Low Voltage
I
OL
= 1 mA
50
mV
V
OH
Output High Voltage
I
OH
= 1 mA
3.1
V
V
OH
Output High Voltage
CPU0:5, APIC0:1
I
OH
= 1 mA
2.2
V
I
OL
Output Low Current
CPU0:5
V
OL
= 1.25V
27
57
97
mA
PCI_F, PCI1:7
V
OL
= 1.5V
20.5
53
139
mA
APIC0:1
V
OL
= 1.25V
40
85
140
mA
REF0:2
V
OL
= 1.5V
25
37
76
mA
48MHz
V
OL
= 1.5V
25
37
76
mA
I
OH
Output High Current
CPU0:5
V
OL
= 1.25V
25
55
97
mA
PCI_F, PCI1:7
V
OL
= 1.5V
31
55
189
mA
IOAPIC
V
OL
= 1.25V
40
87
155
mA
REF0:2
V
OL
= 1.5V
27
44
94
mA
48MHz
V
OL
= 1.5V
27
44
94
mA
Notes:
1.
All clock outputs loaded with 6" 60
transmission lines with 22-pF capacitors.
2.
W130 logic inputs have internal pull-up devices, except SEL100/66# (pull-ups not full CMOS level).
W130
PRELIMINARY
5
AC Electrical Characteristics
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%,V
DDQ2
= 2.5V 5%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
Crystal Oscillator
V
TH
X1 Input Threshold Voltage
[3]
V
DDQ3
= 3.3V
1.65
V
C
LOAD
Load Capacitance, as seen by External Crystal
[4]
14
pF
C
IN,X1
X1 Input Capacitance
[5]
Pin X2 unconnected
28
pF
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance
Except X1 and X2
5
pF
C
OUT
Output Pin Capacitance
6
pF
L
IN
Input Pin Inductance
7
nH
Notes:
3.
X1 input threshold voltage (typical) is V
DD
/2.
4.
The W130 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
5.
X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
DC Electrical Characteristics:
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
CPU Clock Outputs, CPU0:5 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6 MHz
CPU = 100 MHz
Unit
Min.
Typ. Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.25V
15
15.5
10
10.5
ns
t
H
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
t
L
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
200
200
ps
t
SK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
f
ST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
15
15
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