Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

W204

PRELIMINARY

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07264 Rev. *A

Revised December 22, 2002

Features

· Maximized EMI suppression using Cypress's spread

spectrum technology

· Optimized system frequency synthesizer for 440BX and

VIA Apollo Pro-133

· Four copies of CPU output
· Eight copies of PCI clock (synchronous w/CPU output)
· Two copies of 14.318-MHz IOAPIC output and three

buffered copies of 14.318-MHz reference input

· One copy of 48-MHz USB output
· Selectable 24-/48-MHz clock-through-resistor

strapping

· Power management control input pins
· Programmable clock outputs up to 155 MHz via SMBus

interface (32 selectable frequencies)

Key Specifications

Supply Voltages: ..................................... VDDQ3 = 3.3V±5%

VDDQ2 = 2.5V±5%

CPU Cycle to Cycle Jitter: .......................................... 250 ps

CPU0:3 Output Skew: ................................................ 175 ps

PCI_F, PCI1:7 Output Skew: ....................................... 500 ps

CPU to PCI Output Skew: ............... 1.04.0 ns (CPU Leads)

REF0/SEL48#, SCLK,SDATA:........................... 250K pull-up

FS1: ............................................................... 250K pull-down

FS0: ...................................................No pull-up or pull-down

Test mode and output three-state through SMBus interface

Table 1. Pin Selectable Frequency

FS1

FS0

CPU(0:3)

PCI

133.3 MHz

33.3 MHz

105 MHz

35 MHz

100 MHz

33.3 MHz

66.8 MHz

33.3 MHz

Pin Configuration

Block Diagram

VDDQ3

REF0/SEL48#

VDDQ2

APIC0

CPU0

CPU1

CPU2

CPU3

PCI_F

XTAL

PLL Ref Freq

PLL 1

FS0:1

REF1

VDDQ3

Stop

Clock

Control

Stop

Clock

Control

PCI1

PWR_DWN#

Power
Down
Control

PCI2

PCI3

PCI4

PCI5

48MHz

24_48MHz/FS1

PLL2

÷2/÷3

OSC

REF2

VDDQ2

PCI_STOP#

CPU_STOP#

PCI6

PCI7

GND

VDDQ3

GND

APIC1

GND

GNDCORE0/1

VDDCORE0/1

VDDQ3

GND

VDDQ2

SPREAD#

SDATA

Logic

SCLK

REF0/SEL48#

REF1

GND

PCI_F

PCI1

VDDQ3

PCI2

PCI3

GND

PCI4

PCI5

VDDQ3

PCI6

PCI7

GND

VDDQ3

GND

VDDQ3

48MHz

24_48MHz/FS1

GND

VDDQ3

REF2

VDDQ2

APIC0

APIC1

GND

VDDQ2

CPU0

CPU1

GND

VDDQ2

CPU2

CPU3

GND

VDDQ3

GND

PCI_STOP#

CPU_STOP#

PWR_DWN#

SPREAD#

SDATA

SCLK

FS0

Note:

Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.

[1]

W204

PRELIMINARY

Document #: 38-07264 Rev. *A

Page 2 of 16

Pin Definitions

Pin Name

Pin
No.

Pin

Type

Pin Description

CPU0:3

40, 39, 36,

CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.

PCI1:7

8, 10, 11, 13,

14, 16, 17

PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.

PCI_F

Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.

CPU_STOP#

CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW
after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH,
clock outputs CPU0:3 start beginning with a full clock cycle (2-3 CPU clock latency).

PCI_STOP#

PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.

SPREAD#

SPREAD# Input: When brought low this pin activates Spread Spectrum clocking.

APIC0:1

45, 44

I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.

48MHz

48-MHz Output: Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.

24_48MHz/FS1

24-MHz or 48-MHz Output/Frequency Select 1: 24 MHz output when pin 1 is
strapped through 10-K

resistor to VDDQ3. 48-MHz output when pin 1 is strapped

through 10-K

resistor to GND. This pin also serves as the select strap to determine

device operating frequency as described in Table 1.

REF0/SEL48#

I/O

I/O Dual-Function REF0 and SEL48# pin: During power-on, SEL48# input will be
latched which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0
fixed output.

REF1:2

2, 47

Fixed 14.318-MHz Outputs 1 through 2: Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.

FS0

Frequency Selection 0: Selects power-up default CPU clock frequency as shown
in Table 1.

SCLK

Clock pin for SMBus circuitry.

SDATA

I/O

Data pin for SMBus circuitry.

Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.

Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.

PWR_DWN#

Power-Down Control: When this input is LOW, device goes into a low-power stand-
by condition. All outputs are actively held LOW while in power-down. CPU and PCI
clock outputs are stopped LOW after completing a full clock cycle (23 CPU clock
cycle latency). When brought high, CPU, SDRAM and PCI outputs start with a full
clock cycle at full operating frequency (3 ms maximum latency).

VDDQ3

9, 15, 19, 21,

33, 48

Power Connection: Connect to 3.3V supply.

VDDQ2

46, 41, 37

Power Connection: Power supply for APIC0:1 and CPU0:3 output buffers. Connect
to 2.5V.

GND

3, 6, 12, 18,

20, 24, 32,

34, 38, 43

Ground Connections: Connect all ground pins to the common system ground
plane.

W204

PRELIMINARY

Document #: 38-07264 Rev. *A

Page 3 of 16

Overview

The W204, a motherboard clock synthesizer, can provide ei-
ther a 2.5V or 3.3V CPU clock swing making it suitable for a
variety of CPU options. A fixed 48-MHz clock is provided for
other system functions. The device W204 supports spread
spectrum clocking for reduced EMI.

Functional Description

I/O Pin Operation

Pins 1 and 23 are dual-purpose l/O pins. Upon power-up these
pins act as a logic input, allowing the determination of as-
signed device functions. A short time after power-up, the logic
state of the pin is latched and the pin becomes a clock output.
This feature reduces device pin count by combining clock out-
puts with input select pins.

An external 10-K

"strapping" resistor is connected between

the l/O pin and ground or V

. Connection to ground sets a

latch to "0", connection to V

sets a latch to "1". Figure 1 and

Figure 2 show two suggested methods for strapping resistor
connections.

Upon W204 power-up, the first 2 ms of operation is used for
input logic selection. During this period, pins 1 and 23 are

three-stated, allowing the output strapping resistor on the l/O
pin to pull the pin and its associated capacitive clock load to
either a logic HIGH or LOW state. At the end of the 2-ms peri-
od, the established logic "0" or "1" condition of the l/O pin is
then latched. Next the output buffer is enabled which converts
the l/O pin into an operating clock output. The 2-ms timer is
started when V

reaches 2.0V. The input bits can only be

reset by turning V

off and then back on again.

It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock output is 40

(nominal) which is minimally affect-

ed by the 10-K

strap to ground or V

. As with the series

termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or V

should be kept less than two inches in length

to prevent system noise coupling during input logic sampling.

When the clock outputs are enabled following the 2-ms input
period, the associated output frequencies are delivered on the
pins, assuming that V

has stabilized. If V

has not yet

reached full value, output frequency initially may be below tar-
get but will increase to target once V

voltage has stabilized.

In either case, a short output clock cycle may be produced
from the CPU clock outputs when the outputs are enabled.

Power-on

Reset

Timer

Output Three-state

Data

Latch

Hold

W204

Clock Load

10 k

Output

Buffer

(Load Option 1)

10 k

(Load Option 0)

Output

Low

Output Strapping Resistor

Series Termination Resistor

Figure 1. Input Logic Selection Through Resistor Load Option

Power-on

Reset

Timer

Output Three-state

Data

Latch

Hold

W204

Clock Load

10 k

Output

Buffer

Output

Low

Output Strapping Resistor

Series Termination Resistor

Jumper Options

Resistor Value R

Figure 2. Input Logic Selection Through Jumper Option

W204

PRELIMINARY

Document #: 38-07264 Rev. *A

Page 4 of 16

Spread Spectrum Feature

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.

As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:

dB = 6.5 + 9*log

(P) + 9*log

(F)

Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ± 0.5% of the center frequen-
cy. Figure 4 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc-
tion. Contact your local Sales representative for details on
these devices.

Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

Figure 4. Typical Modulation Profile

SSFTG

Typical Clock

Frequency Span (MHz)

1.0

+1.0

0.5%

SS%

+SS%

Amplitud

(dB)

5dB/div

+0.5%

MAX (+0.5%)

MIN (0.5%)

FREQUENCY

W204

PRELIMINARY

Document #: 38-07264 Rev. *A

Page 5 of 16

Serial Data Interface

The W204 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W204 initializes with
default register settings. Therefore, the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the

chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management func-
tions. Table 2 summarizes the control functions of the serial
data interface.

Operation

Data is written to the W204 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.

Table 2. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to un-
used PCI slots.

CPU Clock Frequency
Selection

Provides CPU/PCI frequency selections beyond
the 100- and 66.66-MHz selections that are pro-
vided by the FS0:1 pins. Frequency is changed in
a smooth and controlled fashion.

For alternate microprocessors and power man-
agement options. Smooth frequency transition al-
lows CPU frequency change under normal system
operation.

Output Three-state

Puts all clock outputs into a high impedance state. Production PCB testing.

Test Mode

All clock outputs toggle in relation to X1 input, in-
ternal PLL is bypassed. Refer to Table 4.

Production PCB testing.

(Reserved)

Reserved function for future device revision or pro-
duction device testing.

No user application. Register bit must be written
as 0.

Table 3. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

Slave Address

11010010

Commands the W204 to accept the bits in Data Bytes 36 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W204 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).

Command
Code

Don't Care

Unused by the W204, therefore bit values are ignored ("Don't Care"). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.

Byte Count

Don't Care

Unused by the W204, therefore bit values are ignored ("Don't Care"). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.

Data Byte 0

Don't Care

Refer to Cypress SDRAM drivers.

Data Byte 1

Data Byte 2

Data Byte 3

Refer to Table 4

The data bits in these bytes set internal W204 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.

Data Byte 4

Data Byte 5

Data Byte 6

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