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Электронный компонент: W208D

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PRELIMINARY
FTG for Integrated Core Logic with 133-MHz FSB
W208D
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07228 Rev. **
Revised September 27, 2001
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology
Low jitter and tightly controlled clock skew
Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
Three copies of CPU clock at 66/100 MHz
Nine copies of 100-MHz SDRAM clocks
Eight copies of PCI clock
Two copies of synchronous APIC clock
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
Two copies of 66-MHz fixed clock
One copy of 14.31818-MHz reference clock
Power down control
I
2
CTM interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, 48-MHz, SDRAM Output Skew: ........................250 ps
CPU, 3V66 Output Skew: ............................................ 175 ps
PCI Output Skew: ........................................................ 500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................0.5 ns
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................0.5 ns
I
2
C is a trademark of Phillips Corporation. Intel is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Functions
SEL133
SEL1
SEL0
Function
X
0
0
Three-state
X
0
1
Test
0
1
0
66-MHz CPU
0
1
1
100-MHz CPU
1
1
0
Reserved
1
1
1
133-MHz CPU
Block Diagram
Pin Configuration
VDDQ3
VDDQ2
CPU2_ITP
PCI0_ICH
XTAL
PLL REF FREQ
PLL 1
X2
X1
REF/SEL133
PCI1:7
USB
DOT
PLL2
OSC
VDDQ3
I
2
C
SDATA
Logic
SCLK
3V66_0:1
CPU0:1
SEL0:1
APIC0:1
Divider,
Delay,
and
Phase
Control
Logic
7
2
VDDQ3
2
2
DCLK
SDRAM0:7
8
PWRDWN#
REF/SEL133*
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDDQ3
GND
GND
W208D
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
USB
DOT
VDDQ3
SEL0
PWRDWN#
SCLK
SDATA
SEL1
Note:
1.
Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
[1]
W208D
PRELIMINARY
Document #: 38-07228 Rev. **
Page 2 of 14
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF/SEL133
1
I/O
Reference Clock/Select 133-MHz FSB: 3.3V 14.318-MHz clock output. This pin
also serves as a strap option for CPU frequency selection. See Table 1 for detailed
descriptions.
X1
3
I
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
X2
4
I
Crystal Output: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
PCI0_ICH,
PCI1:7
11, 12, 13, 15,
16, 18, 19. 20
O
PCI Clock 0 through 7: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via I
2
C interface.
3V66_0:1
7, 8
O
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
USB
25
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs.
DOT
26
O
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
SEL0:1
28, 29
I
Clock Function Selection Pins: LVTTL-compatible input to select device func-
tions. See Table 1 for detailed descriptions.
PWRDWN#
32
I
Power-Down Control: LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW.
CPU2_ITP,
CPU0:1
49, 52, 50
O
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz, depending on the
configuration of SEL0:1 and SEL133. Voltage swing set by V
DDQ2
.
SDRAM0:7,
DCLK
46, 45, 43, 42,
40, 39, 37, 36,
34
O
SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via I
2
C interface.
APIC0:1
55, 54
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by V
DDQ2
.
SDATA
30
I/O
Data pin for I
2
C circuitry.
SCLK
31
I
Clock pin for I
2
C circuitry.
VDDQ3
2, 9, 10, 21, 22,
27, 33, 38, 44
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
VDDQ2
51, 53
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
GND
5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
G
Ground Connections: Connect all ground pins to the common system ground
plane.
W208D
PRELIMINARY
Document #: 38-07228 Rev. **
Page 3 of 14
Overview
The W208D is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/SEL133 is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. If the pin is strapped to a HIGH state
externally, CPU clock outputs will run at 133 MHz. If it is
strapped LOW, CPU clock outputs will be determined by the
status of SEL0:1 input pins. An external 10-k
strapping resis-
tor should be used. Figure 1 shows a suggested method for
strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1 outlines the device functions selectable through
SEL133 and SEL0:1. Specific outputs available at each pin are
detailed in Table 2 below. The SEL0 pin requires a 220
pull-up resistor to 3.3V for the W208D to sense the maximum
host bus frequency of the processor and configure itself ac-
cordingly.
Notes:
2.
Provided for board-level "bed of nails" testing.
3.
"Normal" mode of operation.
4.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5.
Required for DC output impedance verification.
6.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W208D
V
DD
Clock Load
10 k
Output
Buffer
(Load Option 1)
10k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Whitney Truth Table
SEL133
SEL1
SEL0
CPU
SDRAM
3V66
PCI
48MHz
REF
APIC
Notes
X
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2
X
0
1
TCLK/4
TCLK/4
TCLK/6
TCLK/12
TCLK/2
TCLK
TCLK/12
4, 5
0
1
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
0
1
1
100 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
1
1
0
Reserved
1
1
1
133 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
W208D
PRELIMINARY
Document #: 38-07228 Rev. **
Page 4 of 14
Offsets Among Clock Signal Groups
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W208D when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is oper-
ating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
CPU 66 Period
SDRAM 100 Period
Hub-PCI
Figure 2. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM Clock)
40 ns
30 ns
20 ns
10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
SDRAM 100 Period
CPU 100 Period
Hub-PCI
Figure 3. Group Offset Waveforms (100-MHz CPU/100-MHz SDRAM Clock)
40 ns
30 ns
20 ns
10 ns
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC 33-MHz
Figure 4. Group Offset Waveform (133-MHz CPU/100-MHz SDRAM)
0 ns
40 ns
30 ns
20 ns
10 ns
W208D
PRELIMINARY
Document #: 38-07228 Rev. **
Page 5 of 14
Power Down Control
W208D provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
Notes:
8.
Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
9.
PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W208D.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate "don't care" states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Table 3. W208D Maximum Allowed Current
W208
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
= 2.625V
All static inputs = V
DDQ3
or V
SS
Max. 3.3V supply consumption
Max. discrete cap loads
V
DDQ3
= 3.465V
All static inputs = V
DDQ3
or V
SS
Powerdown Mode
(PWRDWN# = 0)
100
A
300
A
Full Active 66 MHz
SEL133, SEL1:0 = 010 (PWRDWN# =1)
70 mA
280 mA
Full Active 100 MHz
SEL133, SEL1:0 = 011 (PWRDWN# =1)
100 mA
280 mA
Full Active 133 MHz
SEL133, SEL1:0 = 111 (PWRDWN# =1)
TBD
TBD
1
2
Center
0ns
25ns
50ns
75ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 5. W208D PWRDWN# Timing Diagram
[8, 9, 10, 11]