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Электронный компонент: W238-02H

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FTG for Integrated Core Logic with 133-MHz FSB
W238-02
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07103 Rev. *A
Revised December 26, 2002
1W238-02
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology
Low jitter and tightly controlled clock skew
Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
Two copies of CPU clock at 66/100/133 MHz
Thirteen copies of SDRAM clocks at 100/133 MHz
Five copies of PCI clock compliant to PCI spec 2-1 and
capable of driving a maximum load of 40 pF
One copy of synchronous APIC clock
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
Three copies of 66-MHz fixed clock
One copy of 14.31818-MHz reference clock
Power down control
SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, 48-MHz, SDRAM Output Skew:........................250 ps
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................0.5 ns
Table 1. Pin Selectable Functions
Tristate# FSEL1
FSEL0
Function
SDRAM
0
X
0
Three -State
Three-State
0
X
1
Test
Test
1
0
0
66 MHz
100 MHz
1
0
1
100 MHz
100 MHz
1
1
0
133 MHz
133 MHz
1
1
1
133 MHz
100 MHz
Block Diagram
Pin Configuration
VDDQ3
VDDQ2
PCI0_ICH
XTAL
PLL REF FREQ
PLL 1
X2
X1
REF/FSEL1
PCI1:4
USB
DOT
PLL2
OSC
VDDQ3
SMBus
SDATA
Logic
SCLK
3V66_0:1
CPU0:1
FSEL0:1
APIC0:1
Divider,
Delay,
and
Phase
Control
Logic
4
2
VDDQ3
2
2
SDRAM0:12
13
PWRDWN#/TRISTATE#
APIC
VDDQ2
GND
REF/FSEL1
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
3V66_AGP
GND
PCI_ICH
PCI1
PCI2
VDDQ3
GND
PCI3
PCI4
GNDA
VDDA
SCLK
SDATA
W238-
02
GND
VDDQ2
CPU0
CPU1
GND
SDRAM0
SDRAM1
VDDQ3
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
GND
VDDQ3
USB
DOT
GND
SDRAM12
PWRDWN#/TRISTATE#
FSEL0
3V66_AGP
W238-02
Document #: 38-07103 Rev. *A
Page 2 of 18
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF/FSEL1
4
I/O
Reference Clock/Function Select: 3.3V 14.318-MHz clock output. This pin also
serves as a strap option for CPU frequency selection. See Table 1 for detailed
descriptions.
X1
6
I
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
X2
7
I
Crystal Output: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
PCI0_ICH,
PCI1:4
14, 15, 16, 19,
20
O
PCI Clock 0 through 4: 3.3V 33-MHz PCI clock outputs. PCI1:4 can be individually
turned off via SMBus interface.
3V66_0:1
3V66_AGP
10, 11, 12
O
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
USB
28
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs.
DOT
29
O
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
FSEL0
21
I
Clock Function Selection Pins: LVTTL-compatible input (latched) to select de-
vice functions. See Table 1 for detailed descriptions. This is a latched input. The
status of this pin will be ignore after the internal POR.
PWRDWN#/
TRISTATE#
30
I
TRISTATE#/PWRDWN#: During power-up, this pin defaults to the PWRDWN#
input function. This pin can be configured as the TRISTATE# input function by
control register at Byte[3], Bit[1]. This input can be used as the VTT_PWRGD input
to support Intel
VRM 8.5 implementation.
CPU0:1
54, 53
O
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz, depending on the
configuration of FSEL0:1 and TRISTATE#. Voltage swing set by V
DDQ2
.
SDRAM0:12
51, 50, 47, 46,
45, 44, 41, 40,
39, 38, 35, 34,
31
O
SDRAM Clock Outputs: 3.3V outputs running to 133 MHz. SDRAM0:7 can be
individually turned off via SMBus interface.
APIC
1
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by V
DDQ2
.
SDATA
25
I/O
Data pin for SMBus circuitry.
SCLK
24
I
Clock pin for SMBus circuitry.
VDDQ3
5, 9, 17, 27, 33,
37, 43, 49
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
VDDA
23
O
3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to
3.3V
.
VDDQ2
2, 55
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
GNDA
22
G
Ground Connections: Ground for core logic, PLL circuitry
.
GND
3, 8, 13, 18, 26,
32, 36, 42, 48,
52, 56
G
Ground Connections: Connect all ground pins to the common system ground
plane.
W238-02
Document #: 38-07103 Rev. *A
Page 3 of 18
Overview
The W238 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/SEL1 is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. CPU clock outputs will be determined by
the status of FSEL0:1 input pins. An external 10-k
strapping
resistor should be used. Figure 1 shows a suggested method
for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1 outlines the device functions selectable through
Tristate# and FSEL0:1. Specific outputs available at each pin
are detailed in Table 2 below.
Notes:
1.
Provided for board-level "bed of nails" testing.
2.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
3.
Required for DC output impedance verification.
4.
"Normal" mode of operation.
5.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
6.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W238
V
DD
Clock Load
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Solano Truth Table
Tristate#
FSEL1 FSEL0
CPU
SDRAM
3V66
PCI
48MHz
REF
APIC
Notes
0
X
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
X
1
TCLK/4
TCLK/4
TCLK/6
TCLK/12
TCLK/2
TCLK
TCLK/12
2, 3
1
0
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
4, 5, 6
1
0
1
100 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
4, 5, 6
1
1
1
133 MHz
133MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
1, 3, 5
1
1
1
133 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
1, 3, 5
W238-02
Document #: 38-07103 Rev. *A
Page 4 of 18
How to use PD# input to support VTT_PWRGD
The PD# input can be used to support the VTT_PWRGD sig-
nal specified in the Intel VRM 8.5 specification. The
VTT_PWRGD is used to indicated that the frequency select
output pins (BSEL[0:1]) from the CPU are valid and the clock
generator can use them to determine the CPU FSB frequency.
The assertion of PD# input pin during initial power-up will delay
the start of the PLL, keep all the multiplexed I/O pins as input
and keep all the output inactive. The functionality of PD# will
allow the system designer to use this input to support the
VTT_PWRGD output from the VRM 8.5 module. Please refer
to the Figure 2 for power-up sequence details.
3.3V & 2.5V
PD# (connected to
VTT_PWRGD)
Outputs
Input Latch
(pin 4 & pin21)
1 ms
PLL & Output
Synchronization
Figure 2. Power-up sequence with PD# (VTT_PWRGD) hold LOW
W238-02
Document #: 38-07103 Rev. *A
Page 5 of 18
Offsets Among Clock Signal Groups
Figure 3 and Figure 4 represent the phase relationship among
the different groups of clock outputs from W238 when it is pro-
viding a 66-MHz CPU clock and a 100-MHz CPU clock, re-
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase
with SDRAM clock outputs.
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
CPU 66 Period
SDRAM 100 Period
Hub-PCI
Figure 3. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM)
40 ns
30 ns
20 ns
10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
0 ns
SDRAM 100 Period
CPU 100 Period
Hub-PCI
Figure 4. Group Offset Waveforms (100-MHz CPU/100-MHz SDRAM)
40 ns
30 ns
20 ns
10 ns