PRELIMINARY
Spread Spectrum FTG for VIA K7 Chipset
W310
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07258 Rev. **
Revised September 27, 2001
Features
Single-chip system frequency synthesizer for VIA K7
chipset
Pin compatible with W210, W230 and W230-03
Programmable clock output frequency with less than
1 MHz increment
Integrated fail-safe Watchdog Timer for system recov-
ery
Automatically switch to HW selected or SW pro-
grammed clock frequency when Watchdog Timer time-
out
Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength for CPU, SDRAM and PCI
output clocks
Programmable output skew between CPU, PCI and
SDRAM
Maximized EMI Suppression using Cypress's Spread
Spectrum technology
Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ...........................................175 ps
PCI to PCI Output Skew: ..............................................500 ps
V
DD
: .........................................................................3.3V 5%
SDRAMIN to SDRAM0:12 Delay: ...........................3.7 ns typ.
Table 1. Mode Input Table
Mode
Pin 2
0
CPU_STOP#
1
REF0
Input Address
CPU_CS
CPUT0 (MHz)
PCI 0:5
(MHz)
FS
3
FS
2
FS
1
FS
0
1
1
1
1
100.0
33.3
1
1
1
0
100.0
33.3
1
1
0
1
100.0
33.3
1
1
0
0
95.0
31.7
1
0
1
1
133.3
33.3
1
0
1
0
133.3
33.3
1
0
0
1
133.3
33.3
1
0
0
0
102.0
34.0
0
1
1
1
104.0
34.6
0
1
1
0
106.0
35.3
0
1
0
1
107.0
35.6
0
1
0
0
108.0
36.0
0
0
1
1
109.0
36.3
0
0
1
0
110.0
36.6
0
0
0
1
111.0
37.0
0
0
0
0
112.0
37.3
W310
PRELIMINARY
Document #: 38-07258 Rev. **
Page 2 of 24
Block Diagram
Pin Configuration
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[
1]
VDDQ3
REF0/(CPU_STOP#)
PCI0/MODE
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS0
VDDQ3
Stop
Clock
Control
PCI2
PCI3
PCI4
48MHz/FS2
24_48MHz/FS3
PLL2
2,3,4
OSC
PWRDWN#
VDDQ3
PCI5
SMBus
SDATA
Logic
SCLK
I/O Pin
Control
SDRAM0:12
SDRAMIN
13
VDDQ3
PCI1/FS1
CPUT0
2
CPU_CS
CPUC0
VDDQ3
REF0/(CPU_STOP#)*
GND
X1
X2
VDDQ3
PCI0/MODE*
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
SCLK
W
310
REF1/FS0*
GND
CPU_CS
GND
CPUC0
CPUT0
VDDQ3
RST#
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS2*
24_48MHz/FS3^
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SMBus
{
Logic
Reset
RST#
W310
PRELIMINARY
Document #: 38-07258 Rev. **
Page 3 of 24
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPUT0,
CPUC0,
43, 44
O
(open-
drain)
CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs
for the K7 processor.
CPU_CS
46
O
CPU Clock Output for Chipset: CPU_CS is the push-pull clock output for the
chipset. It has the same phase relationship as CPUT0.
PCI2:5
10, 11, 12, 13
O
PCI Clock Outputs 2 through 5: 3.3V 33-MHz PCI clock outputs. Frequency is
set by FS0:3 inputs or through serial data interface, see Table 2 and Table 5 for
details.
PCI1/FS1
8
I/O
Fixed PCI Clock Output/Frequency Select 1: 3.3V 33-MHz PCI clock outputs.
As an output, frequency is set by FS0:3 inputs or through serial data interface. This
pin also serves as a power-on strap option to determine device operating frequen-
cy as described in Table 2 and Table 5.
PCI0/MODE
7 I/O
Fixed PCI Clock Output/Mode: 3.3V 33-MHz PCI clock outputs. As an output,
frequency is set by the FS0:3 inputs or through serial data interface, see Table 2
and Table 5. This pin also serves as a power-on strap option to determine the
function of pin 2, see Table 1 for details.
RST#
41
O
(open-
drain)
Reset# Output: Open drain system reset output.
48MHz/FS2
26
I/O
48-MHz Output/Frequency Select 2: 3.3V 48-MHz non-spread spectrum output.
This pin also serves as a power on strap option to determine device operating
frequency as described in Table 2 and Table 5.
24_48MHz/
FS3
25
I/O
24_48MHz Output/Frequency Select 3: 3.3V 24 or 48MHz non-spread spectrum
output. This pin also serves as a power-on strap option to determine device oper-
ating frequency as described in Table 2 and Table 5.
REF1/FS0
48
I/O
Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock.
This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 2 and Table 5.
REF0/
CPU_STOP#
2
I/O
Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined
by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPU_CS
to logic 0. When this pin is configured as an output, this pin becomes a 3.3V
14.318-MHz output clock.
SDRAMIN
15
I
SDRAM Buffer Input Pin: Reference input for SDRAM buffer.
SDRAM0:12
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17, 40
O
SDRAM Outputs: These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input.
SCLK
24
I
Clock pin for SMBus circuitry.
SDATA
23
I/O
Data pin for SMBus circuitry.
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
1, 6, 14, 19,
27, 30, 36, 42
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect
to 3.3V supply
GND
3, 9, 16, 22,
33, 39, 45, 47
G
Ground Connections: Connect all ground pins to the common system ground
plane.
W310
PRELIMINARY
Document #: 38-07258 Rev. **
Page 4 of 24
Overview
The W310 was developed as a single-chip device to meet the
clocking needs of VIA K7 core logic chip sets. In addition to the
typical outputs provided by a standard FTG, the W310 adds a
thirteenth output buffer, supporting SDRAM DIMM modules in
conjunction with the chipset.
Functional Description
I/O Pin Operation
Pins 7, 8, 25, 26, and 48 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power-
up, the logic state of each pin is latched and the pins become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-k
"strapping" resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to "0," connection to V
DD
sets a latch to "1." Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W310 power-up, the first 2 ms of operation are used for
input logic selection. During this period, the five I/O pins (7, 8,
25, 26, 48) are three-stated, allowing the output strapping re-
sistor on the l/O pins to pull the pins and their associated ca-
pacitive clock load to either a logic HIGH or LOW state. At the
end of the 2-ms period, the established logic "0" or "1" condi-
tion of the l/O pin is latched. Next the output buffer is enabled
converting the l/O pins into operating clock outputs. The 2-ms
timer starts when V
DD
reaches 2.0V. The input bits can only
be reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock outputs is <40
(nominal), which is minimally
affected by the 10-K
strap to ground or V
DD
. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W310
V
DD
Clock Load
R
10 K
Output
Buffer
(Load Option 1)
10 K
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W310
V
DD
Clock Load
R
10 k
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
Resistor Value R
W310
PRELIMINARY
Document #: 38-07258 Rev. **
Page 5 of 24
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions.
Figure 4 details the Cypress spreading pattern.
Spread Spectrum clocking is activated or deactivated through
the serial data.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
SSFTG
Typical Clock
A
m
plit
ude (
d
B)
Spread
Spectrum
Enabled
EMI Reduction
Non-
Spread
Speactrum
Am
p
litu
d
e
(
d
B
)
Frequency Span (MHz)
Center Spread
Frequency Span (MHz)
Down Spread
Figure 4. Typical Modulation Profile
MAX (0%)
MIN (0.5%)
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
FREQ
UENCY
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