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Электронный компонент: W320-04X

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200-MHz Spread Spectrum Clock Synthesizer/Driver
with Differential CPU Outputs
W320-04
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07010 Rev. *B
Revised January 8, 2002
2W320-04
Features
Benefits
Compliant with Intel
CK-Titan clock synthesizer/driver
specifications
Supports next-generation Pentium
processors using
differential clock drivers
Multiple output clocks at different frequencies
-- Three pairs of differential CPU outputs, up to 200 MHz
-- Ten synchronous PCI clocks, three free-running
-- Six 3V66 clocks
-- Two 48-MHz clocks
-- One reference clock at 14.318 MHz
-- One VCH clock
Motherboard clock generator
-- Supports multiple CPUs and a chipset
-- Support for PCI slots and chipset
-- Supports AGP, DRCG reference, and Hub Link
-- Supports USB host controller and graphic controller
-- Supports ISA slots and I/O chip
Spread Spectrum clocking (down spread)
Enables reduction of electromagnetic interference (EMI)
and overall system cost
Power-down features (PCI_STOP#, CPU_STOP#
PWR_DWN#)
Enables ACPI-compliant designs
Three Select inputs (Mode select and IC Frequency
Select)
Supports up to four CPU clock frequencies
OE and Test Mode support
Enables ATE and "bed of nails" testing
56-pin SSOP package and 56-pin TSSOP package
Widely available standard package enables lower cost
Logic Block Diagram
SSOP and TSSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
VDD_REF
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
XTAL_IN
XTAL_OUT
GND_REF
25
26
27
28
49
52
51
50
53
56
55
54
PCI0
PCI5
66BUFF2/3V66_4
GND_3V66
PCI_STOP#
S2
GND_CPU
CPU_STOP#
PCI_F2
GND_PCI
GND_3V66
VDD_CORE
VDD_ 48 MHz
MULT0#
VDD_CPU
REF
PCI_F0
PCI_F1
VDD_PCI
GND_PCI
PCI1
PCI2
PCI3
VDD_PCI
PCI4
PCI6
VDD_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66IN/3V66_5
PWR_DWN#
3V66_0
VDD_3V66
3V66_1/VCH
GND_ 48 MHz
DOT
USB
GND_IREF
IREF
CPU#2
CPU2
VDD_CPU
CPU#1
CPU1
CPU#0
CPU0
S0
S1
GND_CORE
PWR_GD#
SCLK
SDATA
W3
20-0
4
VDD_REF
CPU0:2
CPU#0:2
PCI_F0:2
XTAL
PLL Ref Freq
X2
X1
REF
VDD_PCI
USB (48MHz)
VCH_CLK/ 3V66_1
OSC
VDD_CPU
CPU_STOP#
SCLK
PCI0:6
PCI_STOP#
Stop
Clock
Control
Stop
Clock
Control
PLL 1
SMBus
Logic
DOT (48MHz)
PWR_DWN#
S0:2
VDD_48MHz
SDATA
VDD_3V66
3V66_0
3V66_2:4/
Divider
Network
3V66_5/ 66IN
PWR
PWR
PWR
PWR
PWR
PLL 2
PWR
66BUFF0:2
Gate
PWR_GD#
Pin Configurations
/2
W320-04
Document #: 38-07010 Rev. *B
Page 2 of 18
Pin Summary
Name
Pins
Description
REF
56
3.3V 14.318-MHz clock output.
XTAL_IN
2
14.318-MHz crystal input.
XTAL_OUT
3
14.318-MHz crystal input.
CPU, CPU# [0:2]
44, 45, 48, 49, 51, 52
Differential CPU clock outputs.
3V66_0
33
3.3V 66-MHz clock output.
3V66_1/VCH
35
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66IN/3V66_5
24
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from
internal VCO.
66BUFF [2:0] /3V66 [4:2]
21, 22, 23
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal
VCO.
PCI_F [0:2]
5, 6, 7,
33-MHz clocks divided down from 66Input or divided down from 3V66.
PCI [0:6]
10, 11, 12, 13, 16, 17, 18
PCI clock outputs divided down from 66Input or divided down from
3V66.
USB
39
Fixed 48-MHz clock output.
DOT
38
Fixed 48-MHz clock output.
S2
40
Special 3.3V 3-level input for Mode selection.
S1, S0
54, 55
3.3V LVTTL inputs for CPU frequency selection.
IREF
42
A precision resistor is attached to this pin, which is connected to the
internal current reference.
MULT0
43
3.3V LVTTL input for selecting the current multiplier for the CPU
outputs.
PWR_DWN#
25
3.3V LVTTL input for Power_Down# (active LOW).
PCI_STOP#
34
3.3V LVTTL input for PCI_STOP# (active LOW).
CPU_STOP#
53
3.3V LVTTL input for CPU_STOP# (active LOW).
PWRGD#
28
3.3V LVTTL input is a level sensitive strobe used to determine when
S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active
LOW). Once PWRGD# is sampled LOW, the status of this output will
be ignored.
SDATA
29
SMBus compatible SDATA.
SCLK
30
SMBus compatible SCLK.
VDD_REF, VDD_PCI,
VDD_3V66, VDD_CPU
1, 8, 14, 19, 32, 46, 50
3.3V power supply for outputs.
VDD_48 MHz
37
3.3V power supply for 48 MHz.
VDD_CORE
26
3.3V power supply for PLL.
GND_REF, GND_PCI,
GND_3V66, GND_IREF,
VDD_CPU
4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs.
GND_CORE
27
Ground for PLL.
W320-04
Document #: 38-07010 Rev. *B
Page 3 of 18
Function Table
[1]
S2
S1
S0
CPU
(MHz)
3V66[0:1]
(MHz)
66BUFF[0:2]/
3V66[2:4]
(MHz)
66IN/3V66_5
(MHz)
PCI_F/PCI
(MHz)
REF0(MHz)
USB/DOT
(MHz)
Notes:
1
0
0
66 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
0
1
100 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
1
0
200 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
1
1
1
133 MHz
66 MHz
66IN
66 MHz Input
66IN/2
14.318 MHz
48 MHz
2, 3, 4
0
0
0
66 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
0
1
100 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
1
0
200 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
0
1
1
133 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
2, 3, 4
Mid
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1, 5
Mid
0
1
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
7, 8, 5
Mid
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Mid
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Swing Select Functions
Mult0
Board Target Trace/Term Z
Reference R, IREF
=
V
DD
/(3*Rr)
Output Current
V
OH
@ Z
0
50
Rr = 221 1%, IREF = 5.00 mA
I
OH
= 4*IREF
1.0V @ 50
1
50
Rr = 475 1%, IREF = 2.32 mA
I
OH
= 6*IREF
0.7V @ 50
Clock Driver Impedances
Impedance
Buffer Name
V
DD
Range
Buffer Type
Min.
Typ.
Max.
CPU, CPU#
Type X1
50
REF
3.1353.465
Type 5
12
30
55
PCI, 3V66, 66BUFF
3.1353.465
Type 5
12
30
55
USB
3.1353.465
Type 3A
12
30
60
DOT
3.1353.465
Type 3B
12
30
60
Clock Enable Configuration
PWR_DWN# CPU_STOP#
PCI_STOP#
CPU
CPU#
3V66
66BUFF
PCI_F
PCI
USB/DOT
VCOS/
OSC
0
X
X
IREF*2
FLOAT
LOW
LOW
LOW
LOW
LOW
OFF
1
0
0
ON
FLOAT
ON
ON
ON
OFF
ON
ON
1
0
1
ON
LOW
ON
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
ON
OFF
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
Note:
1.
TCLK is a test clock driven in on the XTALIN input in test mode.
2.
"Normal" mode of operation
3.
Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
4.
Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5.
Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
6.
Required for DC output impedance verification.
7.
These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
W320-04
Document #: 38-07010 Rev. *B
Page 4 of 18
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various
device functions such as individual clock output buffers, can
be individually enabled or disabled. W320-04 support both
block read and block write operations.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the
ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.
A block write begins with a slave address and a WRITE
condition. The R/W bit is used by the SMBus controller as a
data direction bit. A zero indicates a WRITE condition to the
clock device. The slave receiver address is 11010010 (D2h).
A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the
core logic issues a byte count which describes number of
additional bytes required for the transfer, not including the
command code and byte count bytes. For example, if the host
has 20 data bytes to send, the first byte would be the number
20 (14h), followed by the 20 bytes of data. The byte count byte
is required to be a minimum of 1 byte and a maximum of 32
bytes It may not be 0. Figure 1 shows an example of a block
write.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Data Byte Configuration Map
Start
bit
Slave Address
1 1 0 1 0 0 1 0
R/W 0/1
A
Command
Code
0 0 0 0 0 0 0 0
A Byte Count = N A
Data Byte 0
A
. . . Data Byte N-1 A Stop
bit
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Figure 1. An Example of a Block Write
From Master to Slave
From Slave to Master
Data Byte 0: Control Register (0 = Enable, 1 = Disable)
Bit
Affected
Pin#
Name
Description
Type
Power On
Default
Bit 7
5, 6, 7, 10,
11, 12, 13,
16, 17, 18,
33, 35
PCI [0:6]
CPU[2:0]
3V66[1:0]
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
R/W
0
Bit 6
TBD
TBD
R
0
Bit 5
35
3V66_1/VCH
VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz
R/W
0
Bit 4
44, 45, 48,
49, 51, 52
CPU [2:0]
CPU# [2:0]
CPU_STOP#
Reflects the current value of the external CPU_STOP# pin
R
N/A
Bit 3
10, 11, 12,
13, 16, 17,
18
PCI [6:0]
PCI_STOP#
(Does not affect PCI_F [2:0] pins)
R/W
N/A
Bit 2
S2
Reflects the value of the S2 pin sampled on power-up
R
N/A
Bit 1
S1
Reflects the value of the S1 pin sampled on power-up
R
N/A
Bit 0
S0
Reflects the value of the S1 pin sampled on power-up
R
N/A
W320-04
Document #: 38-07010 Rev. *B
Page 5 of 18
Data Byte 1
Bit
Pin#
Name
Description
Type
Power On
Default
Bit 7
N/A
CPU Mult0 Value
R
N/A
Bit 6
52, 49,
45
CPU0:2
Three-State CPU0:2 during power down
0 = Normal; 1 = Three-stated
R/W
0
Bit 5
44, 45
CPU2
CPU2#
Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running
R/W
0
Bit 4
48, 49
CPU1
CPU1#
Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running
R/W
0
Bit 3
51, 52
CPU0
CPU0#
Allow Control of CPU0 with assertion of CPU_STOP#
0= Not free running; 1 = Free running
R/W
0
Bit 2
44, 45
CPU2
CPU2#
CPU2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
48, 49
CPU1
CPU1#
CPU1Output Enable
1 = Enabled; 0= Disabled
R/W
1
Bit 0
51, 52
CPU0
CPU0#
CPU0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 2
Bit
Pin#
Name
Pin Description
Type
Power On
Default
Bit 7
N/A
N/A
R
0
Bit 6
18
PCI6
PCI6 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 5
17
PCI5
PCI5 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 4
16
PCI4
PCI4 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 3
13
PCI3
PCI3 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 2
12
PCI2
PCI2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
11
PCI1
PCI1 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 0
10
PCI0
PCI0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 3
Bit
Pin#
Name
Pin Description
Type
Power On
Default
Bit 7
38
DOT
DOT 48-MHz Output Enable
R/W
1
Bit 6
39
USB
USB 48-MHz Output Enable
R/W
1
Bit 5
7
PCI_F2
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 4
6
PCI_F1
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 3
5
PCI_F0
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 2
7
PCI_F2
PCI_F2 Output Enable
R/W
1
Bit 1
6
PCI_F1
PCI_F1Output Enable
R/W
1
Bit 0
5
PCI_F0
PCI_F0 Output Enable
R/W
1