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DS1244Y

256K NV SRAM with Phantom Clock

DS1244Y

032697 1/12

FEATURES

Real time clock keeps track of hundredths of seconds,
minutes, hours, days, date of the month, months, and
years

32K x 8 NV SRAM directly replaces volatile static
RAM or EEPROM

Embedded lithium energy cell maintains calendar op-
eration and retains RAM data

Watch function is transparent to RAM operation

Month and year determine the number of days in each
month; volid up to 1200

Standard 28pin JEDEC pinout

Full 10% operating range

Operating temperature range 0

C to 70

Accuracy is better than

1 minute/month @ 25

Over 10 years of data retention in the absence of
power

Available in 120, 150 and 200 ns access time

ORDERING INFORMATION

DS1244YXXX

DS1244Y

120

120 ns access

150

150 ns access

200 ns access

PIN ASSIGNMENT

28PIN ENCAPSULATED PACKAGE

740 MIL EXTENDED

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

A14/RST

A12

DQ0

DQ1

DQ2

GND

PIN DESCRIPTION

Address Inputs

Chip Enable

GND

Ground

Data In/Data Out

Power (+5V)

Write Enable

Output Enable

No Connect

RST

Reset

DESCRIPTION

The DS1244Y 256K NV SRAM with Phantom Clock is a
fully static nonvolatile RAM (organized as 32,768 words
by 8 bits) with a builtin real time clock. The DS1244Y
has a selfcontained lithium energy source and control
circuitry which constantly monitors V

for an outof

tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
garbled data in both the memory and real time clock.

The Phantom Clock provides timekeeping information
including hundredths of seconds, seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with less than 31 days, including correction for
leap years. The Phantom Clock operates in either
24hour or 12hour format with an AM/PM indicator.

DS1244Y

032697 2/12

RAM READ MODE

The DS1244Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable) is
active (low). The unique address specified by the 15 ad-
dress inputs (A0-A14) defines which of the 32,768 bytes
of data is to be accessed. Valid data will be available to
the eight data output drivers within t

ACC

(Access Time)

after the last address input signal is stable, providing
that CE and OE (Output Enable) access times and
states are also satisfied. If OE and CE access times are
not satisfied, then data access must be measured from
the later occurring signal (CE or OE) and the limiting pa-
rameter is either t

for CE or t

for OE rather than ad-

dress access.

RAM WRITE MODE

The DS1244Y is in the write mode whenever the WE
and CE signals are in the active (low) state after address
inputs are stable. The latter occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t

) before another cycle can

be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output bus has been enabled (CE and
OE active) then WE will disable the outputs in t

ODW

from

its falling edge.

DATA RETENTION MODE

The DS1244Y provides full functional capability for V

greater than 4.5 volts and write protects by approxi-
mately 4.0 volts. Data is maintained in the absence of
V

without any additional support circuitry. The non-

volatile static RAM constantly monitors V

. Should the

supply voltage decay, the RAM automatically write pro-
tects itself. All inputs to the RAM become "don't care"
and all outputs are high impedance. As V

falls below

approximately 3.0 volts, the power switching circuit con-
nects the lithium energy source to RAM to retain data.
During powerup, when V

rises above approximately

3.0 volts, the power switching circuit connects external
V

to the RAM and disconnects the lithium energy

source. Normal RAM operation can resume after V

exceeds 4.5 volts.

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is established
by pattern recognition on a serial bit stream of 64 bits
which must be matched by executing 64 consecutive
write cycles containing the proper data on DQ0. All ac-
cesses which occur prior to recognition of the 64bit pat-
tern are directed to memory.

After recognition is established, the next 64 read or write
cycles either extract or update data in the Phantom
Clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is ac-
complished with a serial bit stream under control of Chip
Enable (CE), Output Enable (OE), and Write Enable
(WE). Initially, a read cycle to any memory location us-
ing the CE and OE control of the Phantom Clock starts
the pattern recognition sequence by moving a pointer to
the first bit of the 64bit comparison register. Next, 64
consecutive write cycles are executed using the CE and
WE control of the SmartWatch. These 64 write cycles
are used only to gain access to the Phantom Clock.
Therefore, any address to the memory in the socket is
acceptable. However, the write cycles generated to
gain access to the Phantom Clock are also writing data
to a location in the mated RAM. The preferred way to
manage this requirement is to set aside just one ad-
dress location in RAM as a Phantom Clock scratch pad.
When the first write cycle is executed, it is compared to
bit 0 of the 64bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point-
er is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched (this bit pattern
is shown in Figure 1). With a correct match for 64 bits,
the Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next
64 cycles will cause the Phantom Clock to either receive
or transmit data on DQ0, depending on the level of the
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CE cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Phantom Clock.

DS1244Y

032697 3/12

PHANTOM CLOCK
REGISTER INFORMATION

The Phantom Clock information is contained in 8 regis-
ters of 8 bits, each of which is sequentially accessed one
bit at a time after the 64bit pattern recognition se-
quence has been completed. When updating the Phan-
tom Clock registers, each register must be handled in
groups of 8 bits. Writing and reading individual bits with-

in a register could produce erroneous results. These
read/write registers are defined in Figure 2.

Data contained in the Phantom Clock register is in
binary coded decimal format (BCD). Reading and writ-
ing the registers is always accomplished by stepping
through all 8 registers, starting with bit 0 of register 0 and
ending with bit 7 of register 7.

PHANTOM CLOCK REGISTER DEFINITION Figure 1

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

HEX

VALUE

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally dupli-
cated and causing inadvertent entry to the Phantom Clock is less than 1 in 10

. This pattern is sent to the Phantom

Clock LSB to MSB.

DS1244Y

032697 4/12

PHANTOM CLOCK REGISTER DEFINITION Figure 2

0.1 SEC

0099

0059

0112

0107

0131

0112

0099

RANGE

(BCD)

12/24

MONTH

10 YEAR

YEAR

0.01 SEC

0023

10 SEC

SECONDS

10 MIN

MINUTES

A/P

HOUR

OSC

RST

DAY

10 DATE

DATE

MONTH

AMPM/12/24 MODE

Bit 7 of the hours register is defined as the 12 or
24hour mode select bit. When high, the 12hour mode
is selected. In the 12hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24hour mode, bit 5 is
the second 10hour bit (2023 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the
RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the
RESET input pin is ignored. When the RESET bit is set

to logic 0, a low input on the RESET pin will cause the
Phantom Clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator.
When set to logic 1, the oscillator is off. When set to log-
ic 0, the oscillator turns on and the watch becomes op-
erational. These bits are shipped from the factory set to
a logic 1.

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
which will always read logic 0. When writing these loca-
tions, either a logic 1 or 0 is acceptable.

DS1244Y

032697 5/12

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

0.3V to +7.0V

Operating Temperature

C to 70

Storage Temperature

C to +70

Soldering Temperature

260

C for 10 seconds (See Note 13)

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

C to 70

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Power Supply Voltage

4.5

5.0

5.5

Input Logic 1

2.2

+0.3

Input Logic 0

0.3

0.8

DC ELECTRICAL CHARACTERISTICS

C to 70

C; V

= 5V

10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Leakage Current

1.0

+1.0

I/O Leakage Current
CE

1.0

+1.0

Output Current @ 2.4V

1.0

Output Current @ 0.4V

2.0

Standby Current CE = 2.2V

CCS1

5.0

Standby Current CE = V

0.5V

CCS2

3.0

5.0

Operating Current t

CYC

= 200 ns

CC01

DC TEST CONDITIONS

Outputs are open; all voltages are referenced to ground.

CAPACITANCE

= 25

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Capacitance

Input/Output Capacitance

I/O

DS1244Y

032697 6/12

MEMORY AC ELECTRICAL CHARACTERISTICS

C to 70

C; V

= 5.0V

10%)

PARAMETER

SYMBOL

DS1244Y-120

DS1244Y-150

DS1244Y-200

UNITS

NOTES

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Read Cycle Time

120

150

200

Access Time

ACC

120

150

200

OE to Output Valid

100

CE to Output Valid

120

150

200

OE or CE to Output Active

COE

Output High Z from Deselection

100

Output Hold from Address
Change

Write Cycle Time

120

150

200

Write Pulse Width

100

150

Address Setup Time

Write Recovery Time

Output High Z from WE

ODW

Output Active from WE

OEW

Data Setup Time

Data Hold Time from WE

AC TEST CONDITIONS

Output Load:

50 pF + 1TTL Gate

Input Pulse Levels:

0-3V

Timing Measurement Reference Levels
Input:

1.5V

Output:

1.5V

Input Pulse Rise and Fall Times:

5 ns

DS1244Y

032697 7/12

PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS

C to 70

C; V

= 4.5 to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Read Cycle Time

120

CE Access Time

100

OE Access Time

100

CE to Output Low Z

COE

OE to Output Low Z

OEE

CE to Output High Z

OE to Output High Z

ODO

Read Recovery

Write Cycle Time

120

Write Pulse Width

100

Write Recovery

Data Setup Time

Data Hold Time

CE Pulse Width

100

RESET Pulse Width

RST

200

CE High to PowerFail

POWER-DOWN/POWER-UP TIMING

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

CE at V

before PowerDown

Slew from 4.5V to 0V

(CE at V

)

300

Slew from 0V to 4.5V

(CE at V

)

CE at V

after PowerUp

REC

= 25

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Expected Data Retention Time

years

WARNING:

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

DS1244Y

032697 11/12

NOTES:

1. WE is high for a read cycle.

2. OE = V

or V

. If OE = V

during write cycle, the output buffers remain in a high impedance state.

3. t

is specified as the logical AND of CE and WE. t

is measured from the latter of CE or WE going low to the

earlier of CE or WE going high.

4. t

, t

are measured from the earlier of CE or WE going high.

5. These parameters are sampled with a 50 pF load and are not 100% tested.

6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output

buffers remain in a high impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain

in a high impedance state during this period.

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers

remain in a high impedance state during this period.

9. The expected t

is defined as accumulative time in the absence of V

with the clock oscillator running.

10. t

is a function of the latter occurring edge of WE or CE.

11. t

and t

are a function of the first occurring edge of WE or CE.

12. RST (Pin1) has an internal pullup resistor.

13. RealTime Clock Modules can be successfully processed through conventional wavesoldering techniques as

long as temperature exposure to the lithium energy source contained within does not exceed +85

C. Post solder

cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.

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