E
Copyright 1997 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
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DS1283
Watchdog Timekeeper Chip
DS1283
032697 1/5
FEATURES
Keeps track of hundredths of seconds, seconds, min-
utes, hours, days, date of the month, months, and
years; valid leap year compersation up to 2100
Watchdog timer restarts an outofcontrol processor
Alarm function provides notice of real time related oc-
currences
Designed for battery operation
Programmable interrupts and square wave outputs
maintain 28pin JEDEC footprint
All registers are individually addressable via the ad-
dress and data bus
Accuracy is better than
2 minutes/month at 25
C
50 bytes of user nonvolatile RAM
Optional 28pin SOIC surface mount package
Lowpower CMOS circuitry is maintained on less
than 1
A in standby mode
Optional industrial temperature range 40
C to +85
C
DESCRIPTION
The DS1283 Watchdog Timekeeper Chip is a selfcon-
tained real time clock, alarm, watchdog timer, and inter-
val timer in a 28pin JEDEC DIP or 28pin SOIC sur-
face mount package. The DS1283 is specifically
designed to maintain internal operations from a single
low voltage supply. In fact, the only two external compo-
nents required by the DS1283 are a battery and crystal.
For a complete description of operating conditions,
electrical characteristics, bus timing, and pin descrip-
tions other than X1, X2, V
BAT
, V
CC
, RCLR, INTB, and
INTP see the DS1286 Watchdog Timekeeper data
sheet.
PIN ASSIGNMENT
X1
X2
NC
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
DQ7
SQW
V
BAT
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
X1
X2
NC
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
11
12
13
14
15
16
9
10
17
18
19
20
21
22
23
24
25
26
27
28
V
V
SQW
DQ7
DQ6
DQ5
DQ4
DQ3
CC
BAT
INTA
WE
RCLR
OE
INTP
CE
INTB(INTB)
WE
INTB(INTB)
RCLR
OE
INTP
CE
INTA
DS1283
28PIN DIP (600 MIL)
DS1283S
28PIN SOIC (330 MIL)
NOTE: Pin 4 must be left disconnected.
DS1283
032697 2/5
PIN DESCRIPTION
PIN #
NAME
I/O
DESCRIPTION
1
INTA
O
Interrupt Output A
(open drain)
23
X1,X2
I
32.768 KHz Crystal
4
NC
No Connection
5-10
A0-A5
I
Address Inputs:
A5=Pin 5;
A0=Pin 10
11
DQ0
I/O
Data Input/Output
12
DQ1
I/O
Data Input/Output
13
DQ2
I/O
Data Input/Output
14
GND
Ground
15
DQ3
I/O
Data Input/Output
16
DQ4
I/O
Data Input/Output
17
DQ5
I/O
Data Input/Output
18
DQ6
I/O
Data Input/Output
19
DQ7
I/O
Data Input/Output
20
CE
I
Chip Enable
21
INTP
O
Interrupt Output P
(open drain)
22
OE
I
Output Enable
23
SQW
O
Square Wave Output
24
RCLR
I
RAM Clear
25
V
BAT
I
Battery Input
26
INTB
(INTB)
O
Interrupt Output B
(open drain)
27
WE
I
Write Enable
28
V
CC
I
V
CC
Input
PIN DESCRIPTIONS
X1, X2 Connections for a standard 32.768 KHz quartz
crystal. The internal oscillator circuitry is designed for
operation with a crystal having a load capacitance (C
L
)
of 6 pF. The crystal is connected directly to the X1 and
X2 pins. There is no need for external capacitors or
resistors. For more information on crystal selection and
crystal layout considerations, please consult Applica-
tion Note 58, "Crystal Considerations with Dallas Real
Time Clocks."
V
BAT
, V
CC
Inputs for batteries or power supplies
between 5.5 and 2.5 volts. The V
CC
supply voltage
should never exceed V
BAT
+ 0.3 volts. The V
BAT
input is
used to maintain all internal functions while the V
CC
input is used to keep all inputs and outputs functional.
Therefore, to keep the device fully functional, V
BAT
and
V
CC
must be at the same voltage potential. As long as
the supply voltages are between 4.5 and 5.5 volts, the
timing and the input/output levels are guaranteed. In
this mode, the active current drain is 2 mA (CE=V
IL
) and
the standby current drain is 0.5 mA (CE=V
IH
). Data
retention mode occurs when the V
BAT
supply is
between 5.5 and 2.5 volts and the V
CC
supply is
grounded. In the data retention mode the current drain
is less than 1
A maximum at 5.5 volts (CE=V
BAT
0.2
volts). The current drain specifications are stated with
all outputs unloaded.
RCLR The RCLR pin is used to clear (set to logic 1) all
50 bytes of user nonvolatile RAM but does not affect the
registers involved with time, alarm, and watchdog func-
tions. In order to clear the RAM, RCLR must be forced to
an input logic 0 (0.3 to +0.8 volts). The RCLR function
is designed to be used via human interface (shorting to
ground manually or by switch) and not to be driven with
external buffers. This pin is internally pulled up and
should be left floating when not in use.
INTB Interrupt B on the DS1283 operates identical to
interrupt B on the DS1286 except that the sink and
source current is limited to 500
A. This pin should be
pulled up or down if not used.
INTP Interrupt P on the DS1283 was a missing or no
connection pin on the DS1286. This interrupt works in
the same manner as INTA as programmed by the IPSW
bit. However, INTP is also logically ORed with the MSB
of the date register (see Figure 1). This bit is called the
INP bit on the DS1283 and is forced to zero on the
DS1286. When the INP bit (interrupt P bit) is set to log-
ical one, interrupt P will be held active low. When INP is
set to logical zero, INTP is always at the same logic state
as INTA. This pin is an open drain capable of sinking
4 mA.
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