www.docs.chipfind.ru
1 of 20
REV: 101804
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata
.
FEATURES
Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control Circuit,
and Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM; These Registers Reside in
the 16 Top RAM Locations
Century Byte Register (i.e., Y2K Compliant)
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
Precision Power-On Reset
Programmable Watchdog Timer and RTC
Alarm
BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and seconds with Automatic Leap-
Year Compensation Valid Up to the Year
2100
Battery Voltage-Level Indicator Flag
Power-Fail Write Protection Allows for 10%
V
CC
Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
Also Available in Industrial Temperature
Range: -40C to +85C
PIN CONFIGURATIONS
DS1556
1M, Nonvolatile, Y2K-Compliant
Timekeeping RAM
www.maxim-ic.com
RST
V
CC
A15
IRQ/FT
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
DQ4
DQ3
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
DQ2
GND
15
16
18
17
Encapsulated DIP
Dallas
Semiconductor
DS1556
TOP VIEW
IRQ/FT
1
2
3
A15
A16
RST
V
CC
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
N.C.
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
N.C.
X1
GND V
BAT
X2
PowerCap
Module Board
(Uses DS9034PCX PowerCap)
WE
Dallas
Semiconductor
DS1556
PowerCap is a registered trademark of Dallas Semiconductor.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
2 of 20
PIN DESCRIPTION
A0A16
- Address Input
DQ0DQ7
- Data Input/Outputs
IRQ/FT
- Interrupt, Frequency Test Output (Open Drain)
RST
- Power-On Reset Output (Open Drain)
CE
- Chip Enable
OE
- Output Enable
WE
-
Write
Enable
V
CC
- Power Supply Input
GND
-
Ground
N.C.
- No Connection
X1, X2
- Crystal Connection
V
BAT
-
Battery
Connection
ORDERING INFORMATION
PART TEMP
RANGE
OPERATING
VOLTAGE
(V)
PIN-PACKAGE TOP
MARK
DS1556-70
0C to +70C
5
32 EDIP (0.740a)
DS1556-070
DS1556-70IND
-40C to +85C
5
32 EDIP (0.740a)
DS1556-070 IND
DS1556P-70
0C to +70C
5
34 PowerCap
DS1556P-070
DS1556P-70IND
-40C to +85C
5
34 PowerCap
DS1556P-070 IND
DS1556W-120
0C to +70C
3.3
32 EDIP (0.740a)
DS1556W-120
DS1556W-120IND
-40C to +85C
3.3
32 EDIP (0.740a)
DS1556W-120 IND
DS1556WP-120
0C to +70C
3.3
34 PowerCap
DS1556WP-120
DS1556WP-120IND
-40C to +85C
3.3
34 PowerCap
DS1556WP-120 IND
DESCRIPTION
The DS1556 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) with an
RTC alarm, watchdog timer, power-on reset, battery monitor, and 128k x 8 nonvolatile static RAM. User
access to all registers within the DS1556 is accomplished with a byte-wide interface as shown in Figure 1.
The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.
The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is
continuously updated, which occurs regardless of external registers settings to guarantee that accurate
RTC information is always maintained.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
3 of 20
match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery-backed state to serve as a system
wake-up. Either the
IRQ/FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1556 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the
RST output is used
for this function.
The DS1556 also contains its own power-fail circuitry, which automatically deselects the device when the
V
CC
supply enters an out of tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low V
CC
levels.
PACKAGES
The DS1556 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1556P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
Figure 1. Block Diagram
Dallas
Semiconductor
DS1556
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
4 of 20
Table 1. Operating Modes
V
CC
CE OE WE DQ0DQ7 MODE POWER
V
IH
X X
High-Z
Deselect
Standby
V
IL
X V
IL
D
IN
Write Active
V
IL
V
IL
V
IH
D
OUT
Read Active
V
CC
> V
PF
V
IL
V
IH
V
IH
High-Z
Read
Active
V
SO
< V
CC
<V
PF
X X X High-Z
Deselect CMOS
Standby
V
CC
<V
SO
< V
PF
X X X High-Z Data
Retention Battery
Current
DATA-READ MODE
The DS1556 is in the read mode whenever
CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t
AA
after the last address input is stable, providing that
CE and OE access times are
satisfied. If
CE or OE access times are not met, valid data will be available at the latter of chip enable
access (t
CEA
) or at output enable access time (t
OEA
). The state of the data input/output pins (DQ) is
controlled by
CE and OE. If the outputs are activated before t
AA
, the data lines are driven to an
intermediate state until t
AA
. If the address inputs are changed while
CE and OE remain valid, output data
will remain valid for output data hold time (t
OH)
but will then go indeterminate until the next address
access.
DATA-WRITE MODE
The DS1556 is in the write mode whenever
WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of
WE or CE. The addresses must be held valid throughout the
cycle.
CE and WE must return inactive for a minimum of t
WR
prior to the initiation of a subsequent read
or write cycle. Data in must be valid t
DS
prior to the end of the write and remain valid for t
DH
afterward. In
a typical application, the
OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If
OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
WE will then disable the outputs t
WEZ
after
WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point V
PF
(point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
hen V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
SO
, the device power is
switched from V
CC
to the internal backup lithium battery when V
CC
drops below V
PF
. If V
PF
is greater
than V
SO
, the device power is switched from V
CC
to the internal backup lithium battery when V
CC
drops
below V
SO
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
DS1556 1M, Nonvolatile, Y2K-Compliant Timekeeping RAM
5 of 20
BATTERY LONGEVITY
The DS1556 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the V
CC
supply is not present. The capability of this internal power
supply is sufficient to power the DS1556 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25
C with the internal clock
oscillator running in the absence of V
CC
. Each DS1556 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a
level greater than V
PF
, the lithium energy source is enabled for battery backup operation. Actual life
expectancy of the DS1556 will be much longer than 10 years since no internal battery energy is
consumed when V
CC
is present.
INTERNAL BATTERY MONITOR
The DS1556 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 1FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature compensated comparator circuit monitors the level of V
CC
. When V
CC
falls to the power
fail trip point, the
RST signal (open drain) is pulled low. When V
CC
returns to nominal levels, the
RST
signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
PDF 
ZIP