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072601
FEATURES
Two 32-position log-tapers
60dB attenuation range:
1dB per step (12 taps)
2dB per step (12 taps)
3dB per step (8 taps)
90dB low-end attenuation
2-Wire Interface Control
Power Supply: Dual 12V
Maximum Voltage Across Potentiometers:
12V
Standard Resistance Value: 45kW
Packages: 16-Pin SOIC
Operating Temperature: -40
o
C to +85
o
C
ORDERING INFORMATION
DS1808Z-050
16-Pin SOIC -40C to
+85C 45k
DS1808Z-050/T&R 16-Pin SOIC -40C to
+85C 45k
PIN ASSIGNMENT
L1
A0
V
CC
W0
W
H0
CE
H1
L0
V
B
1
12
11
10
9
7
13
15
6
5
4
3
2
14
A2
A1
SCL
SDA
8
GND
16
V
DD
PIN DESCRIPTION
V
CC
- +12V Supply
V
B
- -12V Supply (substrate bias)
V
DD
- 5V Digital Supply
H
0
, H
1
- High-end Terminals
L
0
, L
1
- Low-end Terminals
W
0
, W
1
- Wiper Terminals
SDA
- 2-Wire Serial Data Input/Output
SCL
- 2-Wire Clock Input
/CE
- 2-Wire Interface Enable
GND
- Ground
A0, A1, A2
- Address Pins
DESCRIPTION
The DS1808 is a dual-channel, digitally controlled, log-taper potentiometer. Each potentiometer is
comprised of 32 wiper terminal positions plus a mute position. The device has three accessible
potentiometer terminals that include the high-side terminal (H), the low-side terminal (L), and the wiper
terminal (W). The resolution of the DS1808 is shown in Figure 8 and represents 1dB per step for the first
12 taps, 2dB per step for the next 12 taps and 3dB per step for the bottom 8 taps, providing a total
attenuation range of 60dB. The mute position of the DS1808 provides greater than 90dB of attenuation.
The wiper position on the resistor ladder is selected via a 6-bit register, whose value is controlled by the
industry-standard 2-wire interface. The interface consists of two control signals: SDA and SCL. The
DS1808 is available in a standard 45k
W resistor value. The DS1808 is specified to operate over the
industrial temperature range (-40
o
C to +85
o
C) and is available in the 16-pin SOIC package. The DS1808
was designed for low-cost, stereo volume control applications. The device is specified to operate from
12V
10% supplies and accept a maximum input signal range of 12V.
DS1808
Dual Log Digital Potentiometer
www.maxim-ic.com
16-Pin SOIC (150-mil)
DS1808
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DS1808 BLOCK DIAGRAM
Figure 1
PIN DESCRIPTIONS
V
CC
Power Supply Terminal. This pin acts as the positive rail. The DS1808 will support positive supply
voltages ranging from 5 to 13.2 volts. When V
CC
V
B
is less than 8 volts the series wiper resistance will
increase up to 1k
W. The value of V
DD
should never exceed V
CC
.
V
B
Substrate Bias Supply. This pin acts as a negative rail. The DS1808 will support negative voltages
ranging from 0 to -13.2 volts. When V
CC
V
B
is less than 8 volts the series wiper resistance will increase
up to 1k
W.
V
DD
DC Supply Terminal. 5V DC voltage supply. The value of V
DD
should never exceed V
CC
.
GND Ground Terminal.
SDA 2-wire serial data interface. The serial data pin is for serial data transfer to and from the DS1808.
The pin is open drain and may be wire-ORed with other open drain or open collector interfaces.
SCL 2-wire serial clock interface. The serial clock input is used to clock data into the DS1808 on rising
edges and clock data out on falling edges.
/CE Port Enable Pin. When active (/CE=0), the port inputs SDA and SCL are recognized by the device.
If inactive (/CE=1), the port input pins SDA and SCL are disabled making 2-wire communication
impossible.
Control Logic
W
0
L
0
H
0
L
1
H
1
W
1
0dB
0dB
>90dB
60dB
V
CC
(+12V Supply)
SCL
Power Supply
V
B
(-12V Supply)
60dB
>90dB
SDA
GND
CE
V
DD
(5V Supply)
Address Lines
A0 A2
DS1808
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A0, A1, A2 Address Inputs. These input pins specify the address of the device when used in a multi-
dropped configuration. Up to eight individual DS1808s may be addressed on a single 2-wire bus.
H0, H1 These are the high-end terminals of the potentiometers. For both potentiometers, it is not
required that these terminals be connected to a potential greater than the low-end terminal of the
potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply
voltage, V
CC
, or go below V
B
.
L0, L1 These are the low-end terminals of the potentiometers. It is not required that these terminals be
connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the
potentiometers cannot exceed the power-supply voltage, V
CC
, or go below V
B
.
W0, W1 Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. Voltage
applied to either wiper terminal cannot exceed the power-supply voltage, V
CC
, or go below V
B
.
DS1808
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OPERATION
The DS1808 is a dual-channel, digitally controlled, logarithmic potentiometer. Each potentiometer has
three accessible terminals, which include H
,
L, and W. Between each resistor element is a tap-point that is
multiplexed to the wiper terminal, W. A block diagram of the DS1808 is shown in Figure 1.
Potentiometer Characteristics
The DS1808 is a volatile device and always powers-up with the wiper positions set to the mute position
(33-decimal) with 90-dB of signal attenuation. The resistor section of the DS1808 is composed of two 32-
position resistor arrays that provide a logarithmic attenuation. The resistor section of the DS1808
provides a typical 50k
W end-to-end resistance between the H terminal and the L terminal. The wiper
terminal will have a total possible 34 tap positions. The 34
th
position is considered the mute position and
will provide attenuation in excess of 90dB.
The potentiometers of the DS1808 are closely matched and provide excellent tracking. Interchannel
matching for the device is specified to provide less than 0.5dB. Tap-to-tap tolerances for the device are
specified to provide less than 0.5dB.
Power Supplies
The DS1808 is designed to be powered from dual 12V supplies. The maximum input signal that can be
placed across the potentiometer sections is 12V. The device can also be powered using a single +12V
power source. When using the device in a single supply configuration, V
B
is set to 0V and the maximum
potentiometer input signals are restricted to single supply voltage rails.
Controlling the Potentiometers
All writing and reading to the potentiometers is done with the industry standard 2-wire interface, which
includes pins SDA and SCL.
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a master. The devices that are controlled by the
master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),
controls the bus access, and generates the start and stop conditions. The DS1808 operates as a slave on
the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The
following I/O terminals control the 2-wire serial port: /CE, SDA, SCL, A0, A1, A2. Timing diagrams for
the 2-wire serial port can be found in Figures 2 and 7.
DS1808
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2-WIRE SERIAL PROTOCOL
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data line from high to low while the clock is high
defines a start condition.
Stop data transfer: A change in the state of the data line from low to high while the clock line is high
defines the stop condition.
Data valid: The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line can be changed during
the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between start and stop conditions is not limited and is determined by the master
device. The information is transferred byte-wise and each receiver acknowledges with a 9
th
bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1808 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an "acknowledge" after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the master to generate the stop condition.
1. The following occurs when data is transferred from a master transmitter to a slave receiver. The first
byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
2. The following occurs when data is transferred from a slave transmitter to a master receiver. The
master transmits the first byte (the command/control byte) to the slave. The slave then returns an
acknowledge bit. Next, follows a number of data bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a "not acknowledge" can be returned.
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