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051900
FEATURES
Two linear taper potentiometers
-
DS1845-010 one 10k, 100 position &
one 10k, 256 position
-
DS1845-050 one 10k, 100 position &
one 50k, 256 postition
-
DS1845-100 one 10k, 100 position &
one 100k, 256 position
256 bytes of EEPROM memory
Access to data and potentiometer control via
a 2-wire interface
External Write Enable pin to protect data and
potentiometer settings
Nonvolatile wiper storage in 2 bytes of
address space
Operates from 3V or 5V supplies
Packaging: Flip Chip Package, 16-ball
STPBGA, 14-pin TSSOP
Industrial operating temperature: -40C to
+85C
Programming temperature: 0C to +70C
PIN ASSIGNMENT
PIN DESCRIPTION
V
CC
- 3V or 5V Power Supply Input
GND
- Ground
SDA
- 2-wire Serial Data
Input/Output
SCL
- 2-wire Serial Clock Input
WP
- Write Protect Input
A0, A1, A2
- Address Inputs
H0, H1
- High-End of Potentiometer
L 0, L1 - Low-End of Potentiometer
W0, W1
- Wiper Terminal of
Potentiometer
DESCRIPTION
The DS1845 Dual NV Potentiometer and Memory consists of one
=100-position linear taper
potentiometer, one
=256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire
interface. The device provides an ideal method for setting bias voltages and currents in control
applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration
or calibration data for a specific system or device as well as provide control of the potentiometer wiper
settings. Any type of user information may reside in the first 248 bytes of this memory. The next two
addresses of EEPROM memory are for potentiometer settings and the remaining 6 bytes of memory are
reserved. These reserved and potentiometer registers should not be used for data storage. Access to this
EEPROM is via an industry standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The
wiper position of the DS1845, as well as EEPROM data, can be hardware write-protected using the Write
Protect (WP) input pin.
DS1845
Dual NV Potentiometer and Memory
www.dalsemi.com
SDA 1
14
Vcc
SCL
2
13
H0
A0
3
12
W1
A1
4
11
H1
A2
5 10
L1
WP
6
9
W0
GND
7
8
L0
14-Pin TSSOP (173 mil)
14-Pin Flip Chip (100 x 100 mils)
16-BALL STPBGA (4 x 4 mm)
See Mech. Drawing Section
DS1845
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DS1845 BLOCK DIAGRAM Figure 1
Up to eight DS1845s can be installed on a single 2-wire bus. Access to an individual device is achieved
by using a device address that is determined by the logic levels of address pins A0 though A2.
Additionally, the DS1845 will operate from 3 volt or 5 volt supplies. Three package options are
available: Flip Chip Package, 16-ball STPBGA and 14-pin TSSOP.
PIN DESCRIPTIONS
V
CC
- Power Supply Terminal. The DS1845 will support supply voltages ranging from +2.7 to +5.5 volts.
GND - Ground Terminal.
SDA - 2-wire serial data interface. The serial data pin is for serial data transfer to and from the DS1845.
The pin is open drain and may be wire-ORed with other open drain or open collector interfaces.
SCL - 2-wire serial clock interface. The serial clock input is used to clock data into the DS1845 on rising
edges and clock data out on falling edges.
WP - Write Protect. Write Protect must be connected to GND before either the data in memory or
potentiometer wiper settings may be changed. Write Protect is pulled high internally and must be either
left open or connected to V
CC
if write protection is desired.
A0, A1, A2 - Address Inputs. These input pins specify the address of the device when used in a multi-
dropped configuration. Up to eight individual DS1845s may be addressed on a single 2-wire bus.
VCC
GND
SDA
SCL
WP
A0
A1
A2
H0
W0
L0
H1
W1
L1
248 BYTES
EEPROM
MEMORY
6 RESERVED
BYTES
1 BYTE WIPER
SETTING
POT 0
1 BYTE WIPER
SETTING
POT 1
CONTROL
DATA
POTENTIOMETER 0
2-WIRE
INTERFACE
POTENTIOMETER 1
100
Position
Pot
256
Position
Pot
DS1845
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H0, H1 These are the high-end terminals of the potentiometers. For both potentiometers, it is not
required that these terminals be connected to a potential greater than the low-end terminal of the
potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply
voltage, V
CC
, or go below ground.
L0, L1 These are the low-end terminals of the potentiometers. It is not required that these terminals be
connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the
potentiometers cannot exceed the power-supply voltage, V
CC
, or go below ground.
W0, W1 - Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. The bytes in
EEPROM memory locations F8h and F9h determine each wiper's setting. Voltage applied to either
wiper terminal cannot exceed the power-supply voltage, V
CC
, or go below ground.
MEMORY ORGANIZATION
The DS1845's serial EEPROM is internally organized with 256 words of 1 byte each. Each word requires
an 8-bit address for random word addressing. The byte at address F9h determines the wiper setting for
potentiometer 0, which contains 100 positions. Writing values above 63h to this address sets the wiper to
its uppermost position. The byte at address F8h determines the wiper setting for potentiometer 1, which
contains 256 positions (00h to FFh). Address locations FAh though FFh are reserved and should not be
written.
DEVICE OPERATION
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device.
Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high
periods will indicate a start or stop conditions depending on the conditions discussed below. Refer to the
timing diagram Fig 2 for further details.
Start Condition: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command. Refer to the timing diagram Fig 2 for further details.
Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command places the DS1845 into a low-power mode. Refer to the timing diagram Fig
2 for further details.
Acknowledge:
All address and data byte are transmitted via a serial protocol. The DS1845 pulls the
SDA line low during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode: The DS1845 features a low-power mode that is automatically enabled after power-on,
after a stop command, and after the completion of all internal operations.
2-Wire Interface Reset: After any interruption in protocol, power loss, or system reset, the following
steps reset the DS1845.
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition while SDA is high.
DS1845
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Device Addressing: The DS1845 must receive an 8-bit device address word following a start condition
to enable a specific device for a read or write operation. The address word is clocked into the DS1845
MSB to LSB. The address word consists of Ah (1010) followed by A2, A1, and A0 then the R/W
(READ/WRITE) bit. If the R/W bit is high, a read operation is initiated. The R/W is low, a write
operation is initiated. For a device to become active, the values of A2, A1 and A0 must be the same as
the hard-wired address pins on the DS1845. Upon a match of written and hard-wired addresses, the
DS1845 will output a zero for one clock cycle as an acknowledge. If the address does not match the
DS1845 returns to a low-power mode.
Write Operations: After receiving a matching address byte with the R/W bit set low, the device goes
into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the
device to define the address where the data is to be written. After the reception of this byte, the DS1845
will transmit a zero for one clock cycle to acknowledge the receipt of the address. The master must then
transmit an 8-bit data word to be written into this address. The DS1845 will again transmit a zero for one
clock cycle to acknowledge the receipt of the data. At this point the master must terminate the write
operation with a stop condition. The DS1845 then enters an internally timed write process T
w
to the
EEPROM memory. All inputs are disabled during this byte write cycle.
The DS1845 is capable of an 8-byte page write. A page write is initiated the same way as a byte write,
but the master does not send a stop condition after the 1
st
byte. Instead, after the slave acknowledges
receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.
The master must terminate the write cycle with a stop condition or the data clocked into the DS1845 will
not be latched into permanent memory.
Acknowledge Polling: Once the internally-timed write has started and the DS1845 inputs are disabled,
acknowledge polling can be initiated. The process involves transmitting a start condition followed by the
device address. The R/W bit signifies the type of operation that is desired. The read or write sequence
will only be allowed to proceed if the internal write cycle has completed and the DS1845 responds with a
zero.
Read Operations: After receiving a matching address byte with the R/W bit set high, the device goes
into the read mode of operation. There are three read operations: current address read, random read and
sequential address read.
CURRENT ADDRESS READ
The DS1845 has an internal address register that maintains the address used during the last read or write
operation, incremented by one. This data is maintained as long as V
CC
is valid. If the most recent
address was the last byte in memory, then the register resets to the first address. This address stays valid
between operations as long as power is available.
Once the device address is clocked in and acknowledged by the DS1845 with the R/W bit set to high, the
current address data word is clocked out. The master does not respond with a zero, but does generate a
stop condition afterwards.
DS1845
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RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
and data address bytes are clocked in by the master, and acknowledged by the DS1845, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the read/write bit set high. The DS1845 will acknowledge the device address and serially
clocks out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1845 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1845.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a stop condition. The master does
not respond with a zero.
For a more detailed description of 2-wire theory of operation, refer to the following section.
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a "master." The devices that are controlled by
the master are "slaves." The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1845 operates as
a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for
the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
-
Data transfer may be initiated only when the bus is not busy.
-
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
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