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REV: 040804
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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.
GENERAL DESCRIPTION
The DS21455 and DS21458 are quad monolithic
devices featuring independent transceivers that
can be software configured for T1, E1, or J1
operation. Each is composed of a line interface
unit (LIU), framer, HDLC controllers, and a
TDM backplane interface, and is controlled via
an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21455* is a
direct replacement for the older DS21Q55 quad
MCM device. The DS21458, in a smaller
package (17mm CSBGA) and featuring an
improved controller interface, is software
compatible with the older DS21Q55.
*The JTAG function on the DS21455/DS21458 is a single
controller for all four transceivers, unlike the DS21Q55, which has
a JTAG controller-per-transceiver architecture.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS21455
0C to +70C
256 BGA
(27mm x 27mm)
DS21455N
-40C to +85C
256 BGA
(27mm x 27mm)
DS21458
0C to +70C
256 CSBGA
(17mm x 17mm)
DS21458N
-40C to +85C
256 CSBGA
(17mm x 17mm)
FEATURES
Four Independent Transceivers, Each Having
the Following Features:
Complete T1 (DS1)/ISDN-PRI/J1
Transceiver Functionality
Complete E1 (CEPT) PCM-30/ISDN-
PRI Transceiver Functionality
Short- and Long-Haul Line Interface for
Clock/Data Recovery and Waveshaping
CMI Coder/Decoder
Crystal-Less Jitter Attenuator
Fully Independent Transmit and Receive
Functionality
Dual HDLC Controllers
On-Chip Programmable BERT Generator
and Detector
Internal Software-Selectable Receive-
and Transmit-Side Termination Resistors
for 75/100/120 T1 and E1
Interfaces
Dual Two-Frame Elastic-Store Slip
Buffers that can Connect to
Asynchronous Backplanes Up to
16.384MHz
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Programmable Output Clocks for
Fractional T1, E1, H0, and H12
Applications
Interleaving PCM Bus Operation
8-Bit Parallel Control Port, Multiplexed
or Nonmultiplexed, Intel or Motorola
IEEE 1149.1 JTAG-Boundary Scan
3.3V Supply with 5V Tolerant Inputs and
Outputs
DS21455 Directly Replaces DS21Q55
Signaling System 7 (SS7) Support
RAI-CI, AIS-CI Support
DS21455/DS21458
Quad T1/E1/J1 Transceivers
www.maxim-ic.com
DALLAS is a registered trademark of Dallas Semiconductor Corp.
MAXIM is a registered trademark of Maxim Integrated Products, Inc.
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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DOCUMENT REVISION HISTORY
REVISION CHANGES
040804
New Product Release.
DS21455/DS21458 Quad T1/E1/J1 Transceivers
3 of 270
TABLE OF CONTENTS
1.
DESCRIPTION ................................................................................................................................................9
1.1
S
TANDARDS
...................................................................................................................... 10
2.
FEATURE HIGHLIGHTS...............................................................................................................................11
2.1
G
ENERAL
.......................................................................................................................... 11
2.2
L
INE
I
NTERFACE
................................................................................................................ 11
2.3
C
LOCK
S
YNTHESIZER
........................................................................................................ 11
2.4
J
ITTER
A
TTENUATOR
......................................................................................................... 12
2.5
F
RAMER
/F
ORMATTER
........................................................................................................ 12
2.6
S
YSTEM
I
NTERFACE
........................................................................................................... 13
2.7
HDLC C
ONTROLLERS
....................................................................................................... 13
2.8
T
EST AND
D
IAGNOSTICS
.................................................................................................... 13
2.9
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
.............................................................................. 14
2.10 C
ONTROL
P
ORT
................................................................................................................ 14
3.
BLOCK DIAGRAM ........................................................................................................................................15
4.
DS21455/DS21458 DELTA...........................................................................................................................17
4.1
P
ACKAGE
.......................................................................................................................... 17
4.2
C
ONTROLLER
I
NTERFACE
................................................................................................... 17
4.3
ESIB F
UNCTION
................................................................................................................ 17
4.4
F
RAMER
/LIU I
NTERIM
S
IGNALS
.......................................................................................... 17
5.
PIN FUNCTION DESCRIPTION....................................................................................................................20
5.1
T
RANSMIT
S
IDE
P
INS
......................................................................................................... 20
5.2
R
ECEIVE
S
IDE
P
INS
........................................................................................................... 22
5.3
P
ARALLEL
C
ONTROL
P
ORT
P
INS
........................................................................................ 24
5.4
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
.............................................................................. 26
5.5
JTAG T
EST
A
CCESS
P
ORT
P
INS
........................................................................................ 26
5.6
L
INE
I
NTERFACE
P
INS
........................................................................................................ 27
5.7
S
UPPLY
P
INS
.................................................................................................................... 28
5.8
P
IN
D
ESCRIPTIONS
............................................................................................................ 29
5.9
P
ACKAGES
........................................................................................................................ 39
6.
PARALLEL PORT .........................................................................................................................................41
6.1
R
EGISTER
M
AP
................................................................................................................. 41
7.
SPECIAL PER-CHANNEL REGISTER OPERATION ..................................................................................46
8.
PROGRAMMING MODEL.............................................................................................................................48
8.1
P
OWER
-U
P
S
EQUENCE
...................................................................................................... 49
8.1.1
Master Mode Register........................................................................................................49
8.2
I
NTERRUPT
H
ANDLING
....................................................................................................... 50
8.3
S
TATUS
R
EGISTERS
.......................................................................................................... 50
8.4
I
NFORMATION
R
EGISTERS
.................................................................................................. 51
8.5
I
NTERRUPT
I
NFORMATION
R
EGISTERS
................................................................................ 51
9.
CLOCK MAP .................................................................................................................................................52
10.
T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................53
10.1 T1 C
ONTROL
R
EGISTERS
.................................................................................................. 53
10.2 T1 T
RANSMIT
T
RANSPARENCY
........................................................................................... 58
10.3 AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
............................................................. 59
10.4 T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
................................................. 60
10.5 T1 I
NFORMATION
R
EGISTER
............................................................................................... 62
11.
E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................64
11.1 E1 C
ONTROL
R
EGISTERS
.................................................................................................. 64
11.2 A
UTOMATIC
A
LARM
G
ENERATION
....................................................................................... 68
11.2.1
Auto AIS ...........................................................................................................................68
11.2.2
Auto RAI ...........................................................................................................................68
11.2.3
Auto E-Bit .........................................................................................................................68
11.2.4
G.706 CRC-4 Interworking ............................................................................................68
11.3 E1 I
NFORMATION
R
EGISTERS
............................................................................................ 69
12.
COMMON CONTROL AND STATUS REGISTERS.....................................................................................71
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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13.
I/O PIN CONFIGURATION OPTIONS..........................................................................................................78
14.
LOOPBACK CONFIGURATIONS................................................................................................................80
14.1 P
ER
-C
HANNEL
P
AYLOAD
L
OOPBACK
.................................................................................. 83
15.
ERROR COUNT REGISTERS......................................................................................................................85
15.1 L
INE
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(LCVCR)............................................................ 86
15.1.1
T1 Operation....................................................................................................................86
15.1.2
E1 Operation....................................................................................................................86
15.2 P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR) .......................................................... 88
15.2.1
T1 Operation....................................................................................................................88
15.2.2
E1 Operation....................................................................................................................88
15.3 F
RAMES
O
UT
O
F
S
YNC
C
OUNT
R
EGISTER
(FOSCR) .......................................................... 89
15.3.1
T1 Operation....................................................................................................................89
15.3.2
E1 Operation....................................................................................................................89
15.4 E-B
IT
C
OUNTER
R
EGISTER
(EBCR)................................................................................... 90
16.
DS0 MONITORING FUNCTION ...................................................................................................................91
16.1 T
RANSMIT
DS0 M
ONITOR
R
EGISTERS
................................................................................ 91
16.2 R
ECEIVE
DS0 M
ONITOR
R
EGISTERS
.................................................................................. 92
17.
SIGNALING OPERATION ............................................................................................................................93
17.1 R
ECEIVE
S
IGNALING
.......................................................................................................... 93
17.1.1
Processor-Based Receive Signaling............................................................................94
17.1.2
Hardware-Based Receive Signaling ............................................................................94
17.2 T
RANSMIT
S
IGNALING
...................................................................................................... 100
17.2.1
Processor-Based Transmit Signaling ........................................................................100
17.2.2
Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
17.2.3
Software Signaling Insertion Enable Registers, T1 Mode ......................................106
18.
PER-CHANNEL IDLE CODE GENERATION ............................................................................................108
18.1 I
DLE
C
ODE
P
ROGRAMMING
E
XAMPLES
............................................................................. 109
19.
CHANNEL BLOCKING REGISTERS.........................................................................................................113
20.
ELASTIC STORES OPERATION...............................................................................................................116
20.1 R
ECEIVE
S
IDE
................................................................................................................. 119
20.1.1
T1 Mode .........................................................................................................................119
20.1.2
E1 Mode .........................................................................................................................119
20.2 T
RANSMIT
S
IDE
............................................................................................................... 120
20.2.1
T1 Mode .........................................................................................................................120
20.2.2
E1 Mode .........................................................................................................................120
20.3 E
LASTIC
S
TORES
I
NITIALIZATION
...................................................................................... 120
20.4 M
INIMUM
-D
ELAY
M
ODE
................................................................................................... 121
21.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................................122
22.
T1 BIT ORIENTED CODE (BOC) CONTROLLER.....................................................................................123
22.1 T
RANSMIT
BOC............................................................................................................... 123
22.2 R
ECEIVE
BOC................................................................................................................. 123
23.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY)........................................127
23.1 H
ARDWARE
S
CHEME
(M
ETHOD
1) .................................................................................... 127
23.2 I
NTERNAL
R
EGISTER
S
CHEME
B
ASED
O
N
D
OUBLE
-F
RAME
(M
ETHOD
2) ............................. 127
23.3 I
NTERNAL
R
EGISTER
S
CHEME
B
ASED
O
N
CRC-4 M
ULTIFRAME
(M
ETHOD
3)...................... 130
24.
HDLC CONTROLLERS ..............................................................................................................................141
24.1 B
ASIC
O
PERATION
D
ETAILS
............................................................................................. 141
24.2 HDLC C
ONFIGURATION
................................................................................................... 143
24.2.1
FIFO Control ..................................................................................................................145
24.3 HDLC M
APPING
.............................................................................................................. 146
24.3.1
Receive...........................................................................................................................146
24.3.2
Transmit .........................................................................................................................148
24.3.3
FIFO Information...........................................................................................................153
24.3.4
Receive Packet Bytes Available .................................................................................153
24.3.5
HDLC FIFOS .................................................................................................................154
24.4 R
ECEIVE
HDLC C
ODE
E
XAMPLE
...................................................................................... 155
24.5 L
EGACY
FDL S
UPPORT
(T1 M
ODE
) ................................................................................. 155
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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24.5.1
Receive Section ............................................................................................................155
24.5.2
Transmit Section ...........................................................................................................157
24.6 D4/SLC96 O
PERATION
................................................................................................. 157
25.
LINE INTERFACE UNIT (LIU) ....................................................................................................................158
25.1 LIU O
PERATION
.............................................................................................................. 159
25.2 LIU R
ECEIVER
................................................................................................................ 159
25.2.1
Receive Level Indicator................................................................................................160
25.2.2
Receive G.703 Section 10 Synchronization Signal .................................................160
25.2.3
Monitor Mode.................................................................................................................160
25.3 LIU T
RANSMITTER
........................................................................................................... 161
25.3.1
Transmit Short-Circuit Detector/Limiter .....................................................................161
25.3.2
Transmit Open-Circuit Detector ..................................................................................161
25.3.3
Transmit BPV Error Insertion ......................................................................................162
25.3.4
Transmit G.703 Section 10 Synchronization Signal (E1 Mode).............................162
25.4 MCLK P
RESCALER
......................................................................................................... 162
25.5 J
ITTER
A
TTENUATOR
....................................................................................................... 162
25.6 CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
............................................................................ 163
25.7 LIU C
ONTROL
R
EGISTERS
............................................................................................... 164
25.8 R
ECOMMENDED
C
IRCUITS
................................................................................................ 173
25.9 C
OMPONENT
S
PECIFICATIONS
.......................................................................................... 175
26.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................................179
27.
BERT FUNCTION .......................................................................................................................................186
27.1 BERT R
EGISTER
D
ESCRIPTION
....................................................................................... 187
27.2 BERT R
EPETITIVE
P
ATTERN
S
ET
..................................................................................... 192
27.3 BERT B
IT
C
OUNTER
....................................................................................................... 193
27.4 BERT E
RROR
C
OUNTER
................................................................................................. 194
28.
PAYLOAD ERROR INSERTION FUNCTION ............................................................................................195
28.1 N
UMBER
O
F
E
RROR
R
EGISTERS
...................................................................................... 197
28.1.1
Number Of Errors Left Register ..................................................................................198
29.
INTERLEAVED PCM BUS OPERATION...................................................................................................199
29.1 C
HANNEL
I
NTERLEAVE
M
ODE
........................................................................................... 199
29.2 F
RAME
I
NTERLEAVE
M
ODE
............................................................................................... 199
30.
EXTENDED SYSTEM INFORMATION BUS (ESIB) ..................................................................................202
31.
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER.....................................................................208
32.
FRACTIONAL T1/E1 SUPPORT ................................................................................................................209
33.
USER-PROGRAMMABLE OUTPUT PINS ................................................................................................210
34.
TRANSMIT FLOW DIAGRAMS..................................................................................................................211
35.
JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT .............................................216
35.1 I
NSTRUCTION
R
EGISTER
.................................................................................................. 220
35.2 T
EST
R
EGISTERS
............................................................................................................. 222
35.3 B
OUNDARY
S
CAN
R
EGISTER
............................................................................................ 222
35.4 B
YPASS
R
EGISTER
.......................................................................................................... 222
35.5 I
DENTIFICATION
R
EGISTER
............................................................................................... 222
36.
FUNCTIONAL TIMING DIAGRAMS...........................................................................................................228
36.1 T1 M
ODE
........................................................................................................................ 228
36.2 E1 M
ODE
........................................................................................................................ 238
37.
OPERATING PARAMETERS.....................................................................................................................251
38.
AC TIMING PARAMETERS AND DIAGRAMS..........................................................................................253
38.1 M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
........................................................................ 253
38.2 N
ONMULTIPLEXED
B
US
AC C
HARACTERISTICS
................................................................. 256
38.3 R
ECEIVE
S
IDE
AC C
HARACTERISTICS
.............................................................................. 259
38.4 T
RANSMIT
AC C
HARACTERISTICS
.................................................................................... 265
39.
PACKAGE INFORMATION ........................................................................................................................269
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