E
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
DS2188
T1/CEPT Jitter Attenuator
DS2188
* Service mark of AT&T Communications
021997 1/11
FEATURES
Attenuates clock and data jitter present in T1 or CEPT
lines
Meets the jitter attenuation templates outlined in
TR62411, TRTSY000170, G.735, and G.742
Only one external component required; either a 6.176
MHz (T1) or 8.192 MHz (CEPT) crystal
Selectable buffer size of 128 or 32 bits
Jitter attenuation is easily disabled
Single +5V supply; lowpower CMOS technology
Available in 16pin DIP and 16pin SOIC (DS2188S)
Companion to the DS2186 Transmit Line and
DS2187 Receive Line Interfaces
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RST
DJA
RPOS
RNEG
RCLK
BDS
TEST
XTAL OUT
VSS
VDD
RRPOS
RRNEG
RRCLK
BL
XTAL2
XTAL1
16PIN DIP/SOIC
DESCRIPTION
The DS2188 T1/CEPT Jitter Attenuator Chip contains a
128 X 2bit buffer which, in conjunction with an external
4X crystal, is used to attenuate the incoming jitter pres-
ent in clock and data. The device meets all of the latest
applicable specifications including those outlined in TR
62411 (Accunet* T1.5 Service Description and Interface
Specifications, December 1990), TRTSY000170
(Digital CrossConnect System Requirements and Ob-
jectives, November 1985), and the CCITT Recommen-
dations G.735 and G.742. The DS2188 is compatible
with the DS2180A T1/ISDN Primary Rate Transceiver
and DS2181A CEPT Transceiver and it is the compan-
ion to the DS2187 T1/CEPT Receive Line Interface and
DS2186 T1/CEPT Transmit Line Interface. It can also
be used in conjunction with the DS2190 T1 Network In-
terface Unit.
DS2188
021997 2/11
OVERVIEW
The RCLK input is fed to a 128 x 2bit FIFO where it
drives the write pointer for the positive (RPOS) and neg-
ative (RNEG) data. The read pointer of the FIFO and
RRCLK is generated by dividing the frequency of the
crystal connected to XTAL1 and XTAL2 by four. The fre-
quency of the crystal is adjusted by a DPLL to the long
term average frequency of RCLK. As long as the jitter
present at RCLK is less than 120 unit intervals peakto
peak (UIpp), then the FIFO buffer will be able to absorb
the incoming jitter and it will be attenuated in accor-
dance with TR 62411 (December 1990). In this situa-
tion, the BL (Buffer Limit) pin will remain low. Figures 1
and 2 illustrate the DS2188 Jitter Attenuator perfor-
mance.
If the incoming jitter has excursions greater than 120
UIpp, then the crystal is adjusted to track the shortterm
frequency variations of the incoming signal so that there
is no loss of data. This adjustment is accomplished by
dividing the 4X crystal by either 3 1/2 or 4 1/2 instead of
4. When the incoming jitter is greater than 120UIpp, the
BL pin will transition high. When the incoming jitter re-
turns to less than 120UIpp, the BL pin will return low.
The jitter attenuator in the DS2188 can be disabled by
tying the DJA pin high. When the jitter attenuator is dis-
abled, the FIFO is bypassed and jitter received at RCLK,
RPOS and RNEG is passed through the DS2188 to
RRCLK, RRPOS, and RRNEG. In this situation, the BL
pin has no significance and XTAL OUT will not be co-
herent with RRCLK.
How to use the DS2188 with Dallas Semiconductor's
other T1 and CEPT line interface parts is illustrated in
Figures 3 through 5. Figure 3 illustrates how to use the
DS2188 in the receive path along with a DS2187 Re-
ceive Line Interface. Figure 4 illustrates how to use the
DS2188 in the transmit path with the DS2186 Transmit
Line Interface. Also, see DS2188 Application Note,
"Operation at Speeds Greater than E1" for additional
information.
BUFFER DEPTH SELECT
The buffer size on the DS2188 can be configured to ei-
ther 128 or 32 bits via the BDS pin. If BDS is tied low,
then the buffer depth will be 128 bits and hence can han-
dle input jitter up to 120 UIpp without losing its full atten-
uation capabilities as is described above in the Over-
view. If BDS is tied high, then the buffer depth is
shortened to 32 bits. In this configuration, the DS2188
can handle input jitter up to 28 UIpp without losing its full
jitter attenuation capabilities. The user may wish to limit
the buffer size to 32 bits in applications where through-
put delay is critical or into existing applications that al-
ready have 32 bits of buffer space.
RESET
The buffer on the DS2188 is automatically centered on
powerup. The user can recenter the 128bit (or 32bit)
buffer on demand via the RST pin. The RST pin on the
DS2188 is negativeedge triggered. When this pin tran-
sitions from hightolow, the buffer is recentered. The
RST pin can be held either high or low during operation
of the DS2188; only a negative going signal will initiate a
recentering. In most cases, a reset of the DS2188 will
corrupt data that is currently passing through the buffer.
0 dB
20 dB
40 dB
60 dB
1
JITTER A
TTENUA
TION
(dB)
10
100
10K
100K
1K
FREQUENCY (Hz)
40 Hz
NOMINAL DS2188
PERFORMANCE
G.742
G.735
DS2188
021997 3/11
DS2188 T1 JITTER ATTENUATION PERFORMANCE Figure 1
0 dB
20 dB
40 dB
60 dB
20 Hz
1
10
100
1K
10K
FREQUENCY (Hz)
JITTER A
TTENUA
TION
(dB)
NOMINAL DS2188
PERFORMANCE
TR 62411
CURVE A
TR 62411
CURVE B
DS2188 CEPT JITTER ATTENUATION PERFORMANCE Figure 2
DS2188
021997 4/11
DS2188 IN THE RECEIVE PATH Figure 3
RST
DS2187
DS2188
RTIP
RRING
RCLK
RPOS
RNEG
RCLK
RPOS
RNEG
RRCLK
RRPOS
RRNEG
XTAL1
XTAL2
XTAL OUT
BL
TEST
BDS
DJA
TO DS2180A,
6.176 MHz (T1) or
8.192 MHz (CEPT)
RECEIVE
DSX1 PAIR
DS2141A, DS2181A,
or DS2143
DS2188 IN THE TRANSMIT PATH Figure 4
RST
DS2186
DS2188
TTIP
TRING
TCLK
TPOS
TNEG
RRCLK
RRPOS
RRNEG
RCLK
RPOS
RNEG
XTAL1
XTAL2
XTAL OUT
BL
TEST
BDS
DJA
FROM DS2180A,
6.176 MHz (T1) or
8.192 MHz (CEPT)
TRANSMIT
DSX1 PAIR
DS2141A, DS2181A,
or DS2143
DS2188
021997 5/11
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
DJA
I
Disable Jitter Attenuation. When high, jittered data and clock
at RPOS, RNEG, and RCLK are passed directly to RRPOS,
RRNEG, and RRCLK.
2
RPOS
I
Receive Positive Data Input. Jittered data input. Sampled on
the falling edge of RCLK.
3
RNEG
I
Receive Negative Data Input. Jittered data input. Sampled on
the falling edge of RCLK.
4
RCLK
I
Receive Clock Input. Jittered input 1.544 MHz or 2.048 MHz
clock.
5
BDS
I
Buffer Depth Select.
0 = 128 bits
1 = 32 bits
6
TEST
I
Test Input. In normal applications, this pin should be tied low.
When tied high, used to verify free running frequency of XTAL.
7
XTAL OUT
O
Crystal Frequency Output. Buffered output of the 4X crystal
connected to XTAL1 and XTAL2.
8
V
SS
Ground. 0.0 volts.
9
10
XTAL1
XTAL2
I
O
Crystal Connections. In T1 environments, connect a 6.176
MHz crystal to these pins. In CEPT environments, connect a
8.192 MHz crystal to these pins.
11
BL
O
Buffer Limit. Transitions high when the buffer fills or empties to
within either 4 bits (BDS=0) or 2 bits (BDS=1) of its capacity.
Indicates that the jitter at RCLK is greater than 120UIpp
(BDS=0) or 28UIpp (BDS=1).
12
RST
I
Reset. Negativeedge triggered; a highlow transition will re-
center the buffer. Activation of this pin may corrupt data through
the DS2188.
13
RRCLK
O
Receive Reference Clock. Dejittered 1.544 MHz or 2.048 MHz
clock.
14
RRNEG
O
Receive Reference Negative Data Output. Dejittered data
output. Updated on the rising edge of RRCLK.
15
RRPOS
O
Receive Reference Positive Data Output. Dejittered data
output. Updated on the rising edge of RRCLK.
16
V
DD
Positive Supply. 5.0 volts.
DS2188
021997 6/11
CRYSTAL REQUIREMENTS
The DS2188 must have a crystal connected to the
XTAL1 and XTAL2 pins. For T1 environments, the fre-
quency of this crystal should be 6.176 MHz. For CEPT
environments, the frequency of this crystal should be
8.192 MHz. Table 2 lists some suggested crystal man-
ufacturers that are recommended for use with the
DS2188. Also, see DS2188 Application Note, "Opera-
tion at Speeds Greater than E1" for additional informa-
tion.
CRYSTAL MANUFACTURERS Table 2
MANUFACTURER
PART #
FREQUENCY
JAN Crystal
632300, JC6A14
632300, JC8A14
6.176 MHz
8.192 MHz
MTRON
4575001
4575002
6.176 MHz
8.192 MHz
CRYSTAL SELECTION GUIDELINES FOR THE DS2188
PARAMETER
SPECIFICATION
Parallel resonant frequency
6.176 MHz (T1) or 8.192 MHz (CEPT)
Mode
Fundamental
Load capacitance
14 to 20 pF (16 pF preferred)
Tolerance
50 ppm over 0 to 70
C
Pullability
CL = 10 pF, delta_f = +175 to +250 ppm
CL = 45 pF, delta_f = 175 to 250 ppm
Effective series resistance
40 ohms maximum for 6.176 MHz
30 ohms maximum for 8.192 MHz
Crystal cut
AT
DS2188
021997 7/11
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground
1.0V to +7.0V
Operating Temperature
0
C to 70
C
Storage Temperature
55
C to +125
C
Soldering Temperature
260
C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATIONS
(0
C to 70
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Logic1
V
IH
2.0
V
CC
+0.3
V
1
Logic 0
V
IL
0.3
+0.8
V
1
Supply
V
DD
4.50
5.50
V
NOTE:
1. Does not apply to XTAL1.
CAPACITANCE
(t
A
=25
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
IN
5
pF
Output
C
OUT
10
pF
DC ELECTRICAL CHARACTERISTICS
(0
C to 70
C; V
DD
=5V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Current
I
DD
7
12
mA
1
Input Leakage
I
L
1.0
+1.0
A
2,3
Output Current (2.4V)
I
OH
1.0
mA
3
Output Current (0.4V)
I
OL
+4.0
mA
3
NOTES:
1. RCLK = 1.544 MHz; V
DD
= 5.50; outputs open.
2. V
SS
< V
IN
< V
DD
: XTAL1 = XTAL2 = V
DD
.
3. Does not apply to XTAL1 or XTAL2.
DS2188
021997 8/11
AC ELECTRICAL CHARACTERISTICS
(0
C to 70
C; V
DD
=5V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
RCLK Period
t
P
200
+200
ppm
1
RCLK Pulse Width
t
WH
,t
WL
100
ns
RCLK Rise and Fall Times
t
R
, t
F
50
ns
RPOS, RNEG Setup to RCLK
t
SD
50
ns
RPOS, RNEG Hold from RCLK
t
HD
50
ns
Propagation Delay from RRCLK
to RRPOS, RRNEG Valid
t
PD
50
ns
Propagation Delay from XTAL
OUT to RRCLK
t
PDC
50
ns
2
RST Pulse Width
t
RST
1
s
NOTES:
1. The average period of RCLK must be within
200 ppm of the fundamental frequency of the crystal divided by four.
2. Only valid when the incoming jitter is less than 120UIpp (BDS=0) or 28UIpp (BDS=1).
DS2188
021997 9/11
AC TIMING DIAGRAM Figure 5
RST
RCLK
RPOS, RNEG
RRCLK
RRPOS, RRNEG
RRCLK
XTAL OUT(1)
XTAL OUT(1)
t
PD
t
SD
t
HD
t
R
t
F
t
P
t
WH
t
WL
t
PDC
t
PDC
t
RST
NOTE:
1. The phase relationship between XTAL OUT and RRCLK can be of either form.
DS2188
021997 10/11
DS2188 T1/CEPT JITTER ATTENUATOR 16PIN DIP
A
B
C
E
F
G
H
J
K
D
1
DIM
MIN
MAX
16PIN
PKG
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
0.740
18.80
0.780
19.81
0.240
6.10
0.260
6.60
0.120
3.05
0.140
3.56
0.300
7.62
0.325
8.26
0.015
0.38
0.040
1.02
0.120
3.04
0.140
3.56
0.090
2.29
0.110
2.79
0.320
8.13
0.370
9.40
0.008
0.20
0.012
0.30
0.015
0.38
0.021
0.53
DS2188
021997 11/11
DS2188S T1/CEPT JITTER ATTENUATOR 16PIN SOIC
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
0.004
0.102
0.012
0.30
0.094
2.38
0.105
2.68
0.398
10.11
0.416
10.57
0.009
0.229
0.013
0.33
0.013
0.33
0.019
0.48
A
F
C
E
phi
J
G
K
L
H
B
1
DIM
MIN
MAX
16PIN
PKG
A IN.
MM
B IN.
MM
C IN.
MM
0.402
10.21
0.412
10.46
0.290
7.37
0.300
7.65
0.089
2.26
0.095
2.41
L IN.
MM
0.016
0.40
0.040
1.02
phi
0
8
0.050 BSC
1.27 BSC
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