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REV: 110204
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GENERAL DESCRIPTION
The DS2482-100 is an IC
to 1-Wire
bridge device
that interfaces directly to standard (100kHz max) or
fast (400kHz max) IC masters to perform bi-
directional protocol conversion between the IC
master and any downstream 1-Wire slave devices.
Relative to any attached 1-Wire slave device, the
DS2482-100 is a 1-Wire master. Internal factory
trimmed timers relieve the system host processor
from generating time-critical 1-Wire waveforms,
supporting both standard and Overdrive 1-Wire
communication speeds. To optimize 1-Wire
waveform generation, the DS2482-100 performs slew
rate control on rising and falling 1-Wire edges and
provides additional programmable features to match
drive characteristics to the 1-Wire slave environment.
Programmable strong pullup features support 1-Wire
power delivery to 1-Wire devices such as EEPROMs
and sensors. The DS2482-100 combines these
features with an output to control an external
MOSFET for enhanced strong pullup application. The
IC slave address assignment is controlled by two
binary address inputs, resolving potential conflicts
with other IC slave devices in the system.
APPLICATIONS
Printers
Medical Instruments
Industrial Sensors
Cell Phones, PDAs
TYPICAL OPERATING CIRCUIT
1-Wire line
DS2482-100
IO
PCTLZ
Current Limiting
Resistor
*R
t
*R
P
(IC port)
C
SDA
SCL
AD0
AD1
V
CC
1-Wire
Device
1-Wire
Device
1-Wire
Device
Optional
circuitry
FEATURES
IC Host Interface, Supports 100kHz and 400kHz
IC Communication Speeds
1-Wire Master IO with Selectable Active or
Passive 1-Wire Pullup
Provides Reset/Presence, 8-Bit, Single-Bit, and
Three-Bit 1-Wire IO Sequences
Standard and Overdrive 1-Wire Communication
Speeds
Slew Controlled 1-Wire Edges
Selectable 1-Wire Slave Presence-Pulse Falling
Edge Masking to Control Fast Edges on the
1-Wire Line
Supports Low-Impedance 1-Wire Strong Pullup
for EEPROMs, Temp Sensors, or Other 1-Wire
Slaves that have Momentary High Current
Modes
2 Address Inputs for IC Address Assignment
Wide Operating Range: 2.9V to 5.5V, -40C to
+85C
8-Pin, 150-mil SO Package
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS2482S-100
-40 to +85
C
8 SO (150 mil)
DS2482S-100/T&R
-40 to +85
C
8 SO (150 mil)
PIN CONFIGURATION
1
2
3
4
8
7
6
5
AD0
AD1
PCTLZ
SDA
VCC
IO
GND
SCL
I
2
C is a trademark of Philips Corp. Purchase of I
2
C components of Maxim Integrated Products, Inc., or one of its Associated Companies,
conveys a license under the Philips I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C
Standard Specification as defined by Philips.
1-Wire is a Registered Trademark of Dallas Semiconductor.
DS2482-100
Single-Channel 1-Wire Master
www.maxim-ic.com
DS2482-100: Single-Channel 1-Wire Master
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
-0.5V, +6V
Maximum Current into Any Pin
20mA
Operating Temperature Range
-40C to +85C
Junction Temperature
+150C
Storage Temperature Range
-55C to +125C
Soldering Temperature
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.9V to 5.5V, T
A
= -40C to +85C.)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.3V 2.9
3.3
3.7
Supply Voltage
V
CC
5V 4.5
5.0
5.5
V
Operating Current
I
CC
(Note
1)
0.75 mA
3.3V (Notes 2, 3)
1.9
1-Wire Input High
V
IH1
5V (Notes 2, 3)
3.4
V
3.3V (Notes 2, 3)
0.75
1-Wire Input Low
V
IL1
5V (Notes 2, 3)
1.0
V
1-Wire Weak Pullup Resistor
R
WPU
(Note
4)
800 1675 W
1-Wire Output Low
V
OL1
At 4mA load
0.4
V
Standard (Notes 4, 5)
2.3
2.5
2.7
Active Pullup On Time
t
APUOT
Overdrive (Notes 4, 5)
0.4
0.5
0.6
s
V
CC
3.2V, 1.5mA load
0.3
Strong Pullup Voltage Drop
DV
STRPU
V
CC
5.2V, 3mA load
0.5
V
Standard (3.3V
10%)
1 4.2
3.3V Pulldown Slew Rate
(Note 6)
PD
SRC
Overdrive (3.3V
10%)
5 22.1
V/s
Standard (5.0V
10%)
2 6.5
5V Pulldown Slew Rate
(Note 6)
PD
SRC
Overdrive (5.0V
10%)
10 40
V/s
Standard (3.3V
10%)
0.8 4
3.3V Pullup Slew Rate
(Note 6)
PU
SRC
Overdrive (3.3V
10%)
2.7 20
V/s
Standard (5.0V
10%)
1.3 6
5V Pullup Slew Rate
(Note 6)
PU
SRC
Overdrive (5.0V
10%)
3.4 31
V/s
Power-On Reset Trip Point
V
POR
2.2
V
1-Wire Timing (Note 5). See Figures 3, 5, 6, and 7.
Standard
7.6
8
8.4
Write 1/Read Low Time
t
W1L
Overdrive 0.9
1
1.1
s
Standard 13.3
14
15
Read Sample Time
t
MSR
Overdrive 1.4
1.5
1.8
s
Standard 65.8
69.3
72.8
1-Wire Time Slot
t
slot
Overdrive 9.9
10.5
11.0
s
3.3V to 0V (Note 7)
0.54
3.0
Fall Time High-to-Low at
Standard Speed (Note 6)
5.0V to 0V (Note 7)
0.55
2.2
3.3V to 0V (Note 7)
0.10
0.59
Fall Time High-to-Low at
Overdrive Speed (Note 6)
t
F1
5.0V to 0V (Note 7)
0.09
0.44
s
DS2482-100: Single-Channel 1-Wire Master
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PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Standard 60
64
68
Write-0 Low Time
t
W0L
Overdrive 7.1
7.5
7.9
s
Standard 5.0
5.3
5.6
Write-0 Recovery Time
t
REC0
Overdrive 2.8
3.0
3.2
s
Standard 570
600
630
Reset Low Time
t
RSTL
Overdrive 68.4
72
75.6
s
Standard 66.5
70
73.5
Presence Detect Sample Time
t
MSP
Overdrive 7.1
7.5
7.9
s
Standard 7.6
8
8.4
Sampling for Short and
Interrupt
t
SI
Overdrive 0.7
0.75
0.8
s
Standard 554.8
584
613.2
Reset High Time
t
RSTH
Overdrive 70.3
74
77.7
s
Presence-Pulse Mask Start
t
ppm1
(Note
8)
9.5 10 10.5 s
Presence-Pulse Mask Stop
t
ppm2
(Note
8)
57 60 63
s
Control Pin (PCTLZ)
Output-Low Voltage
V
OLP
V
CC
= 2.9V, 1.2mA load
current
0.4 V
Output-High Voltage
V
OHP
0.4mA load current
V
CC
0.5V
V
IC Pins (Note 9) See Figure 10
V
CC
= 2.9V to 3.7V
0.25
V
CC
LOW Level Input Voltage
V
IL
V
CC
= 4.5V to 5.5V
-0.5
0.22
V
CC
V
HIGH Level Input Voltage
V
IH
0.7
V
CC
V
CC
+
0.5V
V
Hysteresis of Schmitt Trigger
Inputs
V
hys
0.05
V
CC
V
LOW Level Output Voltage at
3mA Sink Current
V
OL
0.4 V
Output Fall Time from V
Ihmin
to
V
ILmax
with a Bus Capacitance
from 10pF to 400pF
t
of
60 250 ns
Pulse Width of Spikes that are
Suppressed by the Input Filter
t
SP
SDA and SCL pins only
50
ns
Input Current Each I/O Pin with
an Input Voltage Between
0.1V
CCmax
and 0.9V
CCmax
I
i
(Notes 10, 11)
-10
10
A
Input Capacitance
C
i
(Note
10)
10 pF
SCL Clock Frequency
f
SCL
0
400 kHz
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated
t
HD:STA
0.6
s
LOW Period of the SCL Clock
t
LOW
1.3
s
HIGH Period of the SCL Clock
t
HIGH
0.6
s
Set-Up Time for a Repeated
START Condition
t
SU:STA
0.6
s
Data Hold Time
t
HD:DAT
(Notes 12, 13)
0.9
s
Data Set-Up Time
t
SU:DAT
(Note
14)
250
ns
Set-Up Time for STOP
Condition
t
SU:STO
0.6
s
DS2482-100: Single-Channel 1-Wire Master
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PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bus Free Time Between a
STOP and START Condition
t
BUF
1.3
s
Capacitive Load for Each Bus
Line
C
b
(Note
15)
400 pF
Oscillator Warm-Up Time
t
OSCWUP
(Note
16)
100
s
Note 1:
Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive.
Note 2:
With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on
threshold V
IL1
may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not
exceed 300pF.
Note 3:
Active pullup guaranteed to turn on between V
IL1MAX
and V
IH1MIN
.
Note 4:
Active or resistive pullup choice is configurable.
Note 5:
Except for t
F1
, all 1-Wire timing specifications and t
APUOT
are derived from the same timing circuit. Therefore, if one of these
parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in
the same direction and by the same degree.
Note 6:
These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew
rate is slightly faster.
Note 7:
Fall time high-to-low (t
F1
) is derived from PD
SRC
, referenced from 0.9 V
CC
to 0.1 V
CC
.
Note 8:
Presence-pulse masking only applies to standard speed.
Note 9:
All IC timing values are referred to V
IHmin
and V
ILmax
levels.
Note 10:
Applies to SDA, SCL, and AD0, AD1.
Note 11:
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 12:
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
Note 13:
The maximum t
HD
:
DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 14:
A fast-mode IC-bus device can be used in a standard-mode IC-bus system, but the requirement t
SU
:
DAT
250ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t
SU
:
DAT
= 1000 + 250 = 1250ns
(according to the standard-mode IC-bus specification) before the SCL line is released.
Note 15:
C
B
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to IC-bus Specification
v2.1 are allowed.
Note 16:
IC communication should not take place for the max t
OSCWUP
time following a power-on reset.
PIN DESCRIPTION
PIN NAME
FUNCTION
1 V
CC
Power Supply Input
2
IO
IO Driver for 1-Wire Line
3 GND
Ground
Reference
4
SCL
IC Serial Clock Input. Must be tied to V
CC
through a pullup resistor.
5
SDA
IC Serial Data Input/Output. Must be tied to V
CC
through a pullup resistor.
6 PCTLZ
Active-low control output for an external P-channel MOSFET to provide extra power to
the 1-Wire line, e.g., for use with 1-Wire devices that require a higher current temporarily
to operate.
7 AD1
8
AD0
IC Address Inputs. Must be tied to V
CC
or GND. These inputs determine the IC slave
address of the device (see Figure 9).
DS2482-100: Single-Channel 1-Wire Master
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Figure 1. Block Diagram
IC
Interface
Controller
SDA
SCL
Config
Register
T-Time OSC
I/O
Controller
Status
Register
Line
XCVR
AD0
AD1
IO
Read Data
Register
PCTLZ
DETAILED DESCRIPTION
The DS2482-100 is a self-timed 1-Wire master, which supports advanced 1-Wire waveform features including
standard and Overdrive speeds, active pullup, strong pullup for power delivery, and presence-pulse masking. Once
supplied with command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication
functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search,
without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function,
presence pulse, 1-Wire short, search direction taken) through the Status register and data through the Read Data
register. The DS2482 communicates with a host processor through its IC bus interface in standard mode or in fast
mode. The logic state of two address pins determines the IC slave address of the DS2482, allowing up to four
devices operating on the same bus segment without requiring a hub.
DEVICE REGISTERS
The DS2482 has three registers that the IC host can read: Configuration, Status, and Read Data. These registers
are addressed by a read pointer. The position of the read pointer, i.e., the register that the host reads in a
subsequent read access, is defined by the instruction that the has DS2482 executed last. The host has read and
write access to the Configuration register to enable certain 1-Wire features.
Configuration Register
The DS2482 supports allows four 1-Wire features that are enabled or selected through the Configuration register.
These features are:
Active Pullup (APU)
Presence Pulse Masking (PPM)
Strong Pullup (SPU)
1-Wire Speed (1WS)
These features can be selected in any combination. While APU, PPM, and 1WS maintain their state, SPU returns
to its inactive state as soon as the strong pullup has ended.
Configuration Register Bit Assignment
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1WS SPU PPM APU 1WS SPU PPM APU
After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration register reads
00h. When writing to the Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
DS2482-100
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