www.docs.chipfind.ru
1
REV: 072403
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata
.
GENERAL DESCRIPTION
The DS26401 is an octal, software-selectable T1, E1
or J1 framer. It is composed of eight framer/formatters
and a system (backplane) interface. Each framer has
an HDLC controller that can be mapped to any DS0
or FDL (T1)/Sa (E1) bit. The DS26401 also includes a
full-feature BERT device, which can be used with any
of the eight T1/E1 ports, and an internal clock adapter
useful for creating synchronous, high frequency
backplane timing. The DS26401 is controlled through
an 8-bit parallel port that can be configured for
nonmultiplexed Intel or Motorola operation.
APPLICATIONS
Line Cards
Routers
Add-Drop Multiplexers
IMA
DSLAMs ATM
Timing Systems
WAN Interface
PBXs
Switches
Customer-Premise
Equipment
Central Office Equipment
Go to
www.maxim-ic.com/telecom
for a complete list of
Telecommunications data sheets, evaluation kits, application
notes, and software downloads.
FEATURES
8 Independent, Full-Featured T1/E1/J1
Framers/Formatters
Independent Transmit and Receive Paths
Flexible Signaling Extraction and Insertion
Alarm Detection and Insertion
Transmit Synchronizer
AMI, B8ZS, HDB3, NRZ Line Coding
Performance Monitor Counters
BOC Message Controller (T1)
Two-Frame Elastic Store Buffers for Each
Transmitter and Receiver
One HDLC Controller per Framer
RAI-CI and AIS-CI Support
Full-Feature BERT can be Mapped to Any Port
Flexible TDM Backplane Supports Bus Rates
from 1.544MHz to 16.384MHz
Internal Clock Generator (CLAD) Supplies
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
JTAG Test Port
Single 3.3V Supply with 5V Tolerant Inputs
17mm x 17mm, 256-Pin BGA (1.00mm Pitch)
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26401
0C to +70C
256 BGA
DS26401N
-40C to +85C
256 BGA
DS26401
Octal T1/E1/J1 Framer
www.maxim-ic.com
DS26401 Octal T1/E1/J1 Framer
2
TABLE OF CONTENTS
1.
APPLICABLE STANDARDS ........................................................................................................7
2.
FEATURES ..................................................................................................................................8
2.1
F
RAMER
/F
ORMATTER
.....................................................................................................................................8
2.2
S
YSTEM
I
NTERFACE
........................................................................................................................................8
2.3
HDLC C
ONTROLLERS
....................................................................................................................................9
2.4
T
EST AND
D
IAGNOSTICS
.................................................................................................................................9
2.5
C
ONTROL
P
ORT
..............................................................................................................................................9
3.
BLOCK DIAGRAMS...................................................................................................................10
4.
SIGNAL LIST (SORTED BY SIGNAL NAME) ............................................................................13
5.
SIGNAL DESCRIPTIONS...........................................................................................................17
5.1
R
ECEIVE
F
RAMER
S
IGNALS
...........................................................................................................................17
5.2
T
RANSMIT
F
RAMER
S
IGNALS
.........................................................................................................................19
5.3
P
ARALLEL
C
ONTROL
P
ORT
............................................................................................................................20
5.4
S
YSTEM
I
NTERFACE
......................................................................................................................................21
5.5
T
EST
............................................................................................................................................................22
6.
REGISTER MAP.........................................................................................................................23
7.
GLOBAL FUNCTIONS...............................................................................................................24
7.1
G
LOBAL
R
EGISTERS
.....................................................................................................................................24
7.2
G
LOBAL
R
EGISTER
D
ESCRIPTION AND
O
PERATION
........................................................................................25
7.3
IBO M
ULTIPLEXER
........................................................................................................................................27
7.4
I
NTERRUPT
T
REE
..........................................................................................................................................37
8.
T1 RECEIVER ............................................................................................................................38
8.1
T1 R
ECEIVER
R
EGISTER
M
AP
.......................................................................................................................38
8.2
T1 R
ECEIVE
F
RAMER
D
ESCRIPTION AND
O
PERATION
.....................................................................................43
8.3
R
ECEIVE
M
ASTER
-M
ODE
R
EGISTER
..............................................................................................................44
8.4
I
NTERRUPT
I
NFORMATION
R
EGISTER
.............................................................................................................44
8.5
T1 R
ECEIVE
C
ONTROL
R
EGISTERS
...............................................................................................................45
8.6
H.100 (CT B
US
) C
OMPATIBILITY
...................................................................................................................50
8.7
T1 R
ECEIVE
S
TATUS AND
I
NFORMATION
........................................................................................................52
8.8
T1 R
ECEIVE
-S
IDE
D
IGITAL
M
ILLIWATT
C
ODE
G
ENERATION
............................................................................63
8.9
T1 E
RROR
C
OUNT
R
EGISTERS
......................................................................................................................64
8.10
DS0 M
ONITORING
F
UNCTION
....................................................................................................................69
8.11
T1 R
ECEIVE
S
IGNALING
O
PERATION
..........................................................................................................70
8.12
T1 R
ECEIVE
P
ER
-C
HANNEL
I
DLE
C
ODE
I
NSERTION
....................................................................................76
8.13
R
ECEIVE
-C
HANNEL
B
LOCKING
O
PERATION
................................................................................................77
8.14
R
ECEIVE
E
LASTIC
S
TORES
O
PERATION
.....................................................................................................78
8.15
F
RACTIONAL
T1 S
UPPORT
(G
APPED
-C
LOCK
M
ODE
)...................................................................................82
8.16
T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
...........................................................................................83
8.17
R
ECEIVE
SLC-96 O
PERATION
...................................................................................................................85
8.18
R
ECEIVE
FDL ...........................................................................................................................................86
8.19
P
ROGRAMMABLE
I
N
-B
AND
L
OOP
-C
ODE
D
ETECTION
...................................................................................87
8.20
R
ECEIVE
HDLC C
ONTROLLER
...................................................................................................................92
8.21
I
NTERLEAVED
PCM B
US
O
PERATION
(IBO) .............................................................................................100
8.22
I
NTERFACING THE
T1 R
X
F
RAMER TO THE
BERT .....................................................................................102
9.
T1 TRANSMIT ..........................................................................................................................104
9.1
T1 T
RANSMIT
R
EGISTER
M
AP
.....................................................................................................................104
DS26401 Octal T1/E1/J1 Framer
3
9.2
T1 T
RANSMIT
F
ORMATTER
D
ESCRIPTION AND
O
PERATION
...........................................................................108
9.3
T
RANSMIT
-M
ASTER
M
ODE
R
EGISTER
..........................................................................................................109
9.4
I
NTERRUPT
I
NFORMATION
R
EGISTERS
.........................................................................................................109
9.5
T1 T
RANSMIT
C
ONTROL
R
EGISTERS
...........................................................................................................110
9.6
T1 T
RANSMIT
S
TATUS AND
I
NFORMATION
....................................................................................................115
9.7
T1 P
ER
-C
HANNEL
L
OOPBACK
.....................................................................................................................118
9.8
T1 T
RANSMIT
DS0 M
ONITORING
F
UNCTION
................................................................................................119
9.9
T1 T
RANSMIT
S
IGNALING
O
PERATION
.........................................................................................................120
9.10
T1 T
RANSMIT
P
ER
-C
HANNEL
I
DLE
C
ODE
I
NSERTION
................................................................................123
9.11
T1 T
RANSMIT
C
HANNEL
B
LOCKING
R
EGISTERS
........................................................................................124
9.12
T1 T
RANSMIT
E
LASTIC
S
TORES
O
PERATION
............................................................................................125
E
LASTIC
S
TORE
D
ELAY
A
FTER
I
NITIALIZATION
........................................................................................................126
9.13
F
RACTIONAL
T1 S
UPPORT
(G
APPED
C
LOCK
M
ODE
) .................................................................................129
9.14
T1 T
RANSMIT
B
IT
O
RIENTED
C
ODE
(BOC) C
ONTROLLER
.........................................................................130
9.15
T1 T
RANSMIT
FDL..................................................................................................................................131
9.16
T
RANSMIT
SLC96 O
PERATION
..............................................................................................................132
9.17
T
RANSMIT
HDLC C
ONTROLLER
...............................................................................................................133
9.18
HDLC T
RANSMIT
E
XAMPLE
.....................................................................................................................141
9.19
P
ROGRAMMABLE
I
N
-B
AND
L
OOP
-C
ODE
G
ENERATOR
................................................................................142
9.20
I
NTERLEAVED
PCM B
US
O
PERATION
(IBO) .............................................................................................144
9.21
I
NTERFACING THE
T1 T
X
F
ORMATTER TO THE
BERT................................................................................146
9.22
T1 T
RANSMIT
S
YNCHRONIZER
.................................................................................................................148
10.
E1 RECEIVER ..........................................................................................................................150
10.1
E1 R
ECEIVER
R
EGISTER
M
AP
.................................................................................................................150
10.2
E1 R
ECEIVE
F
RAMER
D
ESCRIPTION AND
O
PERATION
...............................................................................155
10.3
R
ECEIVE
M
ASTER
M
ODE
R
EGISTER
.........................................................................................................156
10.4
I
NTERRUPT
I
NFORMATION
R
EGISTERS
......................................................................................................157
10.5
E1 R
ECEIVE
C
ONTROL
R
EGISTERS
.........................................................................................................158
10.6
H.100 (CT B
US
) C
OMPATIBILITY
.............................................................................................................162
10.7
E1 R
ECEIVE
S
TATUS AND
I
NFORMATION
..................................................................................................164
10.8
E1 E
RROR
C
OUNT
R
EGISTERS
................................................................................................................175
10.9
DS0 M
ONITORING
F
UNCTION
..................................................................................................................181
10.10
E1 R
ECEIVE
S
IGNALING
O
PERATION
........................................................................................................182
10.11
E1 R
ECEIVE
P
ER
-C
HANNEL
I
DLE
C
ODE
I
NSERTION
..................................................................................187
10.12
R
ECEIVE
C
HANNEL
B
LOCKING
O
PERATION
...............................................................................................188
10.13
R
ECEIVE
E
LASTIC
S
TORES
O
PERATION
...................................................................................................189
E
LASTIC
S
TORE
D
ELAY
A
FTER
I
NITIALIZATION
........................................................................................................192
10.14
F
RACTIONAL
E1 S
UPPORT
(G
APPED
C
LOCK
M
ODE
).................................................................................193
10.15
A
DDITIONAL
S
A
-B
IT AND
S
I
-B
IT
R
ECEIVE
O
PERATION
(E1 M
ODE
).............................................................194
10.16
R
ECEIVE
HDLC C
ONTROLLER
.................................................................................................................200
HDLC R
ECEIVE
E
XAMPLE
.....................................................................................................................................207
10.17
I
NTERLEAVED
PCM B
US
O
PERATION
(IBO) .............................................................................................208
10.18
I
NTERFACING THE
E1 R
X
F
RAMER TO THE
BERT .....................................................................................210
11.
E1 TRANSMIT..........................................................................................................................212
11.1
E1 T
RANSMIT
R
EGISTER
M
AP
.................................................................................................................212
11.2
E1 T
RANSMIT
F
ORMATTER
D
ESCRIPTION AND
O
PERATION
.......................................................................216
11.3
T
RANSMIT
M
ASTER
M
ODE
R
EGISTER
.......................................................................................................217
11.4
I
NTERRUPT
I
NFORMATION
R
EGISTERS
......................................................................................................218
11.5
E1 T
RANSMIT
C
ONTROL
R
EGISTERS
.......................................................................................................219
11.6
A
UTOMATIC
A
LARM
G
ENERATION
............................................................................................................221
11.7
G.706
I
NTERMEDIATE
CRC-4 U
PDATING
(E1 M
ODE
O
NLY
)......................................................................223
11.8
E1 T
RANSMIT
S
TATUS AND
I
NFORMATION
................................................................................................225
11.9
P
ER
-C
HANNEL
L
OOPBACK
.......................................................................................................................228
11.10
E1 T
RANSMIT
DS0 M
ONITORING
F
UNCTION
.............................................................................................229
11.11
E1 T
RANSMIT
S
IGNALING
O
PERATION
......................................................................................................230
11.12
E1 T
RANSMIT
P
ER
-C
HANNEL
I
DLE
C
ODE
I
NSERTION
................................................................................233
DS26401 Octal T1/E1/J1 Framer
4
11.13
E1 T
RANSMIT
C
HANNEL
B
LOCKING
R
EGISTERS
.......................................................................................234
11.14
E1 T
RANSMIT
E
LASTIC
S
TORES
O
PERATION
............................................................................................235
E
LASTIC
S
TORE
D
ELAY
A
FTER
I
NITIALIZATION
........................................................................................................236
11.15
F
RACTIONAL
E1 S
UPPORT
(G
APPED
C
LOCK
M
ODE
).................................................................................239
11.16
A
DDITIONAL
(S
A
)
AND
I
NTERNATIONAL
(S
I
) B
IT
O
PERATION
(E1 M
ODE
) ....................................................240
11.17
T
RANSMIT
HDLC C
ONTROLLER
...............................................................................................................247
11.18
HDLC T
RANSMIT
E
XAMPLE
.....................................................................................................................255
11.19
I
NTERLEAVED
PCM B
US
O
PERATION
(IBO) .............................................................................................256
11.20
I
NTERFACING THE
E1 T
RANSMITTER TO THE
BERT ..................................................................................258
11.21
E1 T
RANSMIT
S
YNCHRONIZER
.................................................................................................................260
12.
BERT........................................................................................................................................262
12.1
BERT R
EGISTERS
..................................................................................................................................262
12.2
BERT D
ESCRIPTION AND
O
PERATION
.....................................................................................................263
12.3
P
ATTERN
G
ENERATION
...........................................................................................................................264
12.4
P
ATTERN
S
YNCHRONIZATION
...................................................................................................................265
12.5
BER C
ALCULATION
.................................................................................................................................265
12.6
E
RROR
G
ENERATION
..............................................................................................................................265
12.7
BERT C
ONTROL
R
EGISTERS
..................................................................................................................267
12.8
BERT S
TATUS
R
EGISTER
.......................................................................................................................271
12.9
P
SEUDORANDOM
P
ATTERN
R
EGISTERS
...................................................................................................272
12.10
C
OUNT
R
EGISTERS
.................................................................................................................................274
12.11
RAM A
CCESS
.........................................................................................................................................275
13.
FUNCTIONAL TIMING .............................................................................................................276
13.1
D
ELAYS
..................................................................................................................................................276
13.2
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
.........................................................................................277
13.3
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
...................................................................................282
13.4
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
.........................................................................................286
13.5
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
...................................................................................288
14.
OPERATING PARAMETERS ...................................................................................................291
15.
TIMING.....................................................................................................................................292
15.1
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
.......................................................................................292
15.2
R
ECEIVER
AC C
HARACTERISTICS
............................................................................................................295
15.3
T
RANSMIT
AC C
HARACTERISTICS
............................................................................................................298
15.4
JTAG I
NTERFACE
T
IMING
.......................................................................................................................301
15.5
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
...................................................................................................301
16.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................302
16.1
TAP C
ONTROLLER
S
TATE
M
ACHINE
........................................................................................................303
16.2
I
NSTRUCTION
R
EGISTER
..........................................................................................................................306
16.3
T
EST
R
EGISTERS
....................................................................................................................................307
17.
PACKAGE INFORMATION ......................................................................................................308
18.
THERMAL INFORMATION ......................................................................................................309
19.
REVISION HISTORY................................................................................................................309
DS26401 Octal T1/E1/J1 Framer
5
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................10
Figure 3-2. Typical PLL Connection..........................................................................................................................11
Figure 3-3. Typical Bipolar Network-Side Interface to Framers................................................................................11
Figure 3-4. Typical NRZ Network-Side Interface to Framers....................................................................................12
Figure 7-1. Internal IBO Multiplexer Equivalent Circuit--4.096MHz .........................................................................28
Figure 7-2. Internal IBO Multiplexer Equivalent Circuit--8.192MHz .........................................................................29
Figure 7-3. Internal IBO Multiplexer Equivalent Circuit--16.394MHz ......................................................................30
Figure 8-1. RSYNC Input in H.100 (CT Bus) Mode ..................................................................................................50
Figure 8-2. TSSYNC Input in H.100 (CT Bus) Mode ................................................................................................51
Figure 8-3. Receive HDLC Example........................................................................................................................99
Figure 9-1. HDLC Message Transmit Example.....................................................................................................141
Figure 10-1. RSYNC Input in H.100 (CT Bus) Mode ..............................................................................................162
Figure 10-2. TSSYNC Input in H.100 (CT Bus) Mode ............................................................................................163
Figure 10-3. Receive HDLC Example....................................................................................................................207
Figure 11-1. HDLC Message Transmit Example....................................................................................................255
Figure 12-1. Shared BERT Block Diagram.............................................................................................................266
Figure 13-1. T1 Receive-Side D4 Timing ...............................................................................................................277
Figure 13-2. T1 Receive-Side ESF Timing .............................................................................................................277
Figure 13-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) .............................................................278
Figure 13-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................278
Figure 13-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................279
Figure 13-6. T1 Receive-Side Interleave Bus Operation, BYTE Mode...................................................................280
Figure 13-7. T1 Receive-Side Interleave Bus Operation, FRAME Mode................................................................281
Figure 13-8. T1 Transmit-Side D4 Timing ..............................................................................................................282
Figure 13-9. T1 Transmit-Side ESF Timing............................................................................................................282
Figure 13-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) ...........................................................283
Figure 13-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ..........................................283
Figure 13-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................284
Figure 13-13. T1 Transmit-Side Interleave Bus Operation, BYTE Mode................................................................284
Figure 13-14. T1 Transmit Interleave Bus Operation, FRAME Mode.....................................................................285
Figure 13-15. E1 Receive-Side Timing ...................................................................................................................286
Figure 13-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................286
Figure 13-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ...........................................287
Figure 13-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ...........................................287
Figure 13-19. E1 Transmit-Side Timing..................................................................................................................288
Figure 13-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................288
Figure 13-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) .........................................289
Figure 13-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................289
Figure 13-23. E1 G.802 Timing...............................................................................................................................290
Figure 15-1. Intel Bus Read Timing (BTS = 0).......................................................................................................293
Figure 15-2. Intel Bus Write Timing (BTS = 0).......................................................................................................293
Figure 15-3. Motorola Bus Read Timing (BTS = 1) ...............................................................................................294
Figure 15-4. Motorola Bus Write Timing (BTS = 1) ...............................................................................................294
Figure 15-5. Receive Framer Timing--Backplane (T1 Mode)...............................................................................295
Figure 15-6. Receive-Side Timing--Elastic Store Enabled (T1 Mode)..................................................................296
Figure 15-7. Receive Framer Timing--Line Side ..................................................................................................297
Figure 15-8. Transmit Formatter Timing--Backplane ...........................................................................................299
Figure 15-9. Transmit Formatter Timing, Elastic Store Enabled ...........................................................................300
Figure 15-10. Transmit Formatter Timing--Line Side ...........................................................................................300
Figure 15-11. JTAG Interface Timing Diagram.......................................................................................................301
Figure 16-1. JTAG Functional Block Diagram ........................................................................................................302
Figure 16-2. Tap Controller State Diagram............................................................................................................303
Document Outline
PDF 
ZIP