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REV: 102704
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GENERAL DESCRIPTION
The DS28E04-100 is a 4096-bit, 1-Wire
EEPROM
chip with seven address inputs. The address inputs
are directly mapped into the 1-Wire 64-bit Device ID
Number to easily enable the host system to identify
the physical location or functional association of the
DS28E04-100 in a multidevice 1-Wire network en-
vironment. The 4096-bit EEPROM array is configured
as 16 pages of 32 bytes with a 32 byte scratchpad to
perform write operations. EEPROM memory pages
can be individually write protected or put in EPROM-
emulation mode, where bits can only be changed
from a 1 to a 0 state. In addition to the memory, the
DS28E04-100 has two general-purpose I/O ports that
can be used for input or to generate level and/or
pulse outputs. Activity registers also capture port
activity for state change monitoring. The DS28E04-
100 communicates over the single-contact 1-Wire
bus. The communication follows the standard Dallas
Semiconductor 1-Wire protocol.
APPLICATIONS
Autoconfiguration of Modular Systems such as
Central-Office Switches, Cellular Base Stations,
Access Products, Optical Network Units, and
PBXs
Accessory/PCB Identification
TYPICAL OPERATING CIRCUIT
PX.Y
C
R
PUP
V
CC
IO V
CC
POL
P1
P0
GND
A0
A6
DS28E04 #1
IO V
CC
POL
P1
P0
GND
A0
A6
DS28E04 #7
RST1 RST0
LED
FEATURES
4096 bits of EEPROM Memory Partitioned into
16 Pages of 256 Bits
Seven Address Inputs for Physical Location
Configuration
Two General-Purpose PIO Pins with Pulse-
Generation Capability
Individual Memory Pages can be Permanently
Write-Protected or put in OTP EPROM-
Emulation Mode ("Write to 0")
Communicates to Host with a Single Digital
Signal at 15.3kbps or 111kbps Using 1-Wire
Protocol
Parasitic or V
CC
Powered
Conditional Search Based on PIO Status or PIO
Activity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Reads and Writes Over a Wide 2.8V to 5.25V
Voltage Range from -40C to +85C
16-Pin, 150-mil SO Package
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS28E04S-100
-40C to +85C 16 SO (150 mils)
DS28E04S-100/T&R -40C to +85C Tape-and-Reel
PIN CONFIGURATION
IO
A4
A5
A6
GND
N.C.
P1
P0
A3
A2
A1
A0
GND
N.C.
V
CC
POL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SO (150 mils)
DS28E04-100
4096-Bit Addressable 1-Wire EEPROM
with PIO
www.maxim-ic.com
Commands, Registers, and Modes are capitalized for
clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
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ABSOLUTE MAXIMUM RATINGS
All Pins: Voltage to GND
-0.5V, +6V
All Pins: Sink Current
20mA
Operating Temperature Range
-40C to +85C
Junction Temperature
+150C
Storage Temperature Range
-40C to +85C
Soldering Temperature
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
PUP
= 2.8V to 5.25V, V
CC
= V
PUP
, floated or grounded, T
A
= -40C to +85C.)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Ground Current
I
GND
(Notes 1, 2, 3)
20
mA
Supply Current
I
CC
V
CC
= V
PUP
(Note 3)
1
mA
Standby Supply Current
I
CCS
Device idle; A0 to A6 floating
11
A
PINS A0 TO A6
Input Low Voltage
V
ILA
(Note 1)
0.30
V
Input High Voltage
V
IHA
V
X
= max(V
PUP
, V
CC
) (Note 1)
V
X
-
0.3V
V
Input Load Current
I
LA
Pin at GND (Note 4)
-1.1
A
POL PIN
Input Low Voltage
V
ILPOL
(Note 1)
0.30
V
Input High Voltage
V
IHPOL
V
X
= max(V
PUP
, V
CC
) (Note 1)
V
X
-
0.3V
V
Leakage Current
I
LKPOL
Pin
at
5.25V
1
A
PIO PINS
Input Low Voltage
V
ILP
(Note 1)
0.30
V
Input High Voltage
V
IHP
V
X
= max(V
PUP
, V
CC
) (Note 1)
V
X
-
0.3V
V
Output Low Voltage at
4mA
V
OLP
(Note 5)
0.4
V
Leakage Current
I
LKP
Pin
at
5.25V
1 A
Minimum Sensed PIO
Pulse
t
PWMIN
(Note
6)
1
10
s
Output Pulse Duration
t
PULSE
(Note
7)
250
1000 ms
IO PIN GENERAL DATA
1-Wire Pullup Resistance
R
PUP
(Notes 1, 8)
0.3 2.2
k
W
Input Capacitance
C
IO
(Notes
3,
9)
100 800 pF
IO pin at V
PUP
, A0 to A6 floating, V
CC
at
GND
0.05 11.00
Input Load Current
I
L
IO pin at V
PUP
, A0 to A6 floating, V
CC
at
V
PUP
0.05 8.25
A
High-to-Low Switching
Threshold
V
TL
(Notes 3, 10, 11)
0.46
4.40
V
Input Low Voltage
V
IL
(Notes 1, 12)
0.3
V
Input High Voltage
V
IH
V
X
= max(V
PUP
, V
CC
) (Note 1)
V
X
-
0.3V
V
Low-to-High Switching
Threshold
V
TH
(Notes 3, 10, 13)
1.0
4.9
V
Switching Hysteresis
V
HY
(Notes 3, 10, 14)
0.21
1.70
V
Output Low Voltage
V
OL
At 4mA Current Load (Note 5)
0.4 V
Standard speed, R
PUP
= 2.2k
W
5
Overdrive speed, R
PUP
= 2.2k
W
2
Recovery Time
(Notes 1, 15)
t
REC
Overdrive speed, directly prior to reset
pulse; R
PUP
= 2.2k
W
5
s
Standard speed (Note 16)
0.5
5.0
Rising-Edge Hold-Off Time
(Note 3)
t
REH
Overdrive speed
Not applicable (0)
s
Standard speed
65
Time Slot Duration
(Note 1)
t
SLOT
Overdrive speed
9
s
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
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PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed, V
PUP
> 4.5V
480
640
Standard speed (Note 17)
504
640
Overdrive speed, V
PUP
> 4.5V
48
80
Reset Low Time (Note 1)
t
RSTL
Overdrive speed (Note 17)
53
80
s
Standard
speed
15 60
Presence-Detect High
Time
t
PDH
Overdrive speed (Note 17)
2
7
s
Standard speed, V
PUP
> 4.5V
1.10
3.75
Standard speed
1.1
7.0
Presence-Detect Fall Time
(Notes 3, 18)
t
FPD
Overdrive speed
0
1.1
s
Standard speed
60
240
Overdrive speed, V
PUP
> 4.5V
8
24
Presence-Detect Low
Time
t
PDL
Overdrive speed (Note 17)
8
26
s
Standard speed, V
PUP
> 4.5V
64
75
Standard
speed
67 75
Presence-Detect Sample
Time (Note 1)
t
MSP
Overdrive speed
8.1
10
s
IO PIN, 1-Wire WRITE
Standard speed
60
120
Write-0 Low Time (Note 1)
t
W0L
Overdrive speed (Note 17)
7
16
s
Standard speed
5
15 -
e
Write-1 Low Time
(Notes 1, 19)
t
W1L
Overdrive speed
1
2 -
e
s
IO PIN, 1-Wire READ
Standard speed
5
15 -
d
Read Low Time
(Notes 1, 20)
t
RL
Overdrive speed
1
2 -
d
s
Standard speed
t
RL
+
d
15
Read Sample Time
(Notes 1, 20)
t
MSR
Overdrive speed
t
RL
+
d
2
s
EEPROM
Programming Current
I
PROG
(Note 21)
1
mA
Programming Time
t
PROG
(Note 22)
10
ms
At +25C
200k
Write/Erase Cycles
(Endurance)
N
CY
At +85C (worst case)
50k
Data Retention
t
DR
At +85C (worst case)
10
years
Note 1:
System requirement.
Note 2:
Maximum instantaneous pulldown current through all pins combined.
Note 3:
Guaranteed by design, simulation only. Not production tested.
Note 4:
This load current is caused by the internal weak pullup, which asserts a logical 1 to address pins that are not connected. The
logical state of the address pins must not change during the execution of ROM function commands during those time slots in
which these bits are relevant.
Note 5:
The I-V characteristic is linear for voltages less than 1V.
Note 6:
Width of the narrowest pulse that trips the activity latch. Back to back pulses that are active for < t
PWMIN
(max) and that have an
intermediate inactive time < t
PWMIN
(max) are not guaranteed to be filtered.
Note 7:
The Pulse function requires that V
CC
power is available; otherwise the command will not be executed.
Note 8:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 9:
Capacitance on the data pin could be 800pF when V
PUP
is first applied. If a 2.2k
W resistor is used to pull up the data line, 2.5s
after V
PUP
has been applied the parasite capacitance will not affect normal communications.
Note 10:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage.
Note 11:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 12:
The voltage on IO needs to be less than or equal to V
ILMAX
whenever the master drives the line low.
Note 13:
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 14:
After V
TH
is crossed during a rising edge on IO, the voltage on IO has to drop by at least V
HY
to be detected as logic '0'.
Note 15:
Applies to a single DS28E04-100 without V
CC
supply, attached to a 1-Wire line.
Note 16:
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been previously reached.
Note 17:
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table.
Note 18:
Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
Note 19:
e represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
.
Note 20:
d represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high threshold of the bus
master.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
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Note 21:
Current drawn during the EEPROM programming interval. If the device does not get V
CC
power, the pullup circuit on IO during the
programming interval should be such that the voltage at IO is greater than or equal to V
PUP
(min). If V
PUP
in the system is close to
Vpup(min) then a low-impedance bypass of R
PUP
that can be activated during programming may need to be added.
Note 22:
The t
PROG
interval begins t
REHmax
after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
or I
CCS
, respectively.
LEGACY VALUES
DS28E04-100 VALUES
PARAMETER
STANDARD SPEED
OVERDRIVE SPEED
STANDARD SPEED
OVERDRIVE SPEED
MIN MAX MIN MAX MIN MAX MIN MAX
t
SLOT
(incl. t
REC
)
61s (undef) 7s (undef) 65s
1)
(undef) 9s
(undef)
t
RSTL
480s (undef) 48s 80s 504s
640s
53s
80s
t
PDH
15s 60s 2s 6s 15s 60s 2s 7s
t
PDL
60s 240s 8s 24s 60s 240s 8s 26s
t
W0L
60s 120s 6s 16s 60s 120s 7s
16s
1)
Intentional change, longer recovery time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
PIN NAME
FUNCTION
1
A3
Address bit input (place value = 8), with weak pullup.
2
A2
Address bit input (place value = 4), with weak pullup.
3
A1
Address bit input (place value = 2), with weak pullup.
4
A0
Least significant address bit input (place value = 1), with weak pullup.
5, 12
GND
Ground Reference
6, 11
N.C.
Not Connected
7 V
CC
Optional power supply for the chip; float or ground if V
CC
power is not available.
8
POL
Power-up polarity (logical state) for P0 and P1; pin has a weak pulldown.
9
P0
Remote-controlled I/O pin, open drain with weak pulldown.
10
P1
Remote-controlled I/O pin, open drain with weak pulldown.
13
A6
Address bit input (place value = 64), with weak pullup.
14
A5
Address bit input (place value = 32), with weak pullup.
15
A4
Address bit input (place value = 16), with weak pullup.
16
IO
1-Wire Bus Interface. Open drain, requires external pullup resistor.
DETAILED DESCRIPTION
The DS28E04-100 combines 4096 bits of EEPROM, a 16-byte control page, two general-purpose PIO pins, seven
external address pins, and a fully featured 1-Wire interface in a single chip. PIO outputs are configured as open-
drain and provide an on-resistance of 100
W max. A robust PIO channel-access communication protocol ensures
that PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the
scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the
scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory
location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this
number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number
guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus and operate independently of each other. The DS28E04-
100 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity. The
DS28E04-100 has an optional V
CC
supply connection. When an external supply is absent, device power is supplied
parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of
the 1-Wire bus power source. Applications of the DS28E04-100 include autoconfiguration and state monitoring of
modular systems such as central-office switches, cellular base stations, access products, optical network units, and
PBXs, and accessory/PC board identification.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
5 of 36
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte
scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the eight
ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip
ROM, 6) Resume, 7) Overdrive-Skip ROM or 8) Overdrive-Match ROM. Upon completion of an Overdrive ROM
command byte executed at standard speed, the device enters Overdrive mode where all subsequent
communication occurs at a higher speed. The protocol required for these ROM function commands is described in
Figure 14. After a ROM function command is successfully executed, the memory/control functions become
accessible and the master may provide any one of the nine Memory/Control Function commands. The protocol for
these commands is described in Figure 9. All data is read and written least significant bit first.
Figure 1. Block Diagram
1-Wire Network
Device ID
Number Register
1-Wire
Function Control
Memory
Function
Control Unit
Special Function
Registers
32-Byte
Scratchpad
Data Memory
16 Pages of
32 Bytes Each
CRC16
Generator
A0
A6
IO
Internal V
DD
PIO
Control Registers
P0
V
CC
P1
POL
Internal V
DD
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