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112299

FEATURES

Flexibly organized as 32k x 32, 64k x 16 or
128k x 8bits

10 years minimum data retention in the
absence of external power

Nonvolatile circuitry transparent to and
independent from host system

Automatic write protection circuitry
safeguards against data loss

Separate control and data signals for each
SRAM allow byte, word or doubleword
access

Fast access time of 70 ns

Full V

± 10% operating range

Employs popular JEDEC standard 72-position
SIMM connector

Extremely thin design built using TSOP-
package IC components

PIN ASSIGNMENT

PIN DESCRIPTION

A0 - A14

- Address Inputs

D0A - D7A

- Data Inputs/Outputs, Byte A

D0B - D7B

- Data Inputs/Outputs, Byte B

D0C - D7C

- Data Inputs/Outputs, Byte C

D0D - D7D - Data Inputs/Outputs, Byte D

CEA

CED

- Chip

Enable

Inputs

WEA

WED

- Write

Enable

Inputs

OEA

OED

- Output

Enable

Inputs

VCC

- +5V Power Supply

GND -

Ground

NC -

Connect

DESCRIPTION

The DS3803 is a self-contained, 1,048,576-bit, nonvolatile static RAM which can be flexibly organized
as 32k x 32, 64k x 16 or 128k x 8. Built using four 32k x 8 SRAMs, four nonvolatile control ICs and four
lithium batteries, this nonvolatile memory contains all necessary control circuitry and lithium energy
sources to maintain data integrity in the absence of power for more than 10 years. The DS3803 employs
the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry.

DS3803

1024k Flexible NV SRAM SIMM

www.dalsemi.com

DS3803 72-Pin SIMM

256K

SR
AM

256K

SR
AM

256K

SR
AM

256K

SR
AM

DS3803

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READ MODE

The DS3803 executes a read cycle whenever

(Write enable) is inactive (high) and

(Chip Enable)

and

(Output Enable) are active (low). The unique address specified by the 15 address inputs (A

) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available

to the data output drivers within t

ACC

(Access Time) after the last address input signal is stable, providing

that

and

(Output Enable) access times are also satisfied. If

and

access times are not

satisfied, then data access must be measured from the later occurring signal and the limiting parameter is
either t

for

or t

for

rather than t

ACC

WRITE MODE

The DS3803 executes a write cycle whenever both

and

signals are in the active (low) state after

address inputs are stable. The later occurring falling edge of

will determine the start of the

write cycle. The write cycle is terminated by the earlier rising edge of

. All address inputs must

be kept valid throughout the write cycle.

must return to the high state for a minimum recovery time

) before another cycle can be initiated. The

control signal should be kept inactive (high) during

write cycles to avoid bus contention. However, if the output drivers are enabled (

and

active),

then

will disable the outputs in t

ODW

from its falling edge.

DATA RETENTION MODE

The DS3803 provides full functional capability for V

greater than 4.5 volts and write-protects by 4.25

volts. Data is maintained in the absence of V

without any additional support circuitry. The nonvolatile

static RAM constantly monitors V

. Should the supply voltage decay, the NV SRAM automatically

write-protects itself, all inputs become don't care, and all outputs become high impedance. As V

falls

below approximately 3.0 volts, power switching circuits connect the lithium energy sources to the RAMs
to retain data. During power-up, when V

rises above approximately 3.0 volts, the power switching

circuits connect external V

to the RAMs and disconnects the lithium energy source. Normal RAM

operation can resume after V

exceeds 4.5 volts.

The DS3803 checks battery status to warn of potential data loss. Each time that V

power is restored to

the DS3803, the battery voltages are checked with precision comparators. If both batteries providing
backup power to a particular SRAM are less than 2.0 volts, the second memory access to that SRAM is
inhibited. Battery status for each SRAM can therefore be determined by a three-step process. First, a read
cycle is performed to any location within that SRAM in order to save the contents of that location. A
subsequent write cycle can then be executed to the same memory location, altering data. If a subsequent
read cycle fails to verify the written data, then battery voltage for that SRAM is less than 2.0V and data is
in danger of being lost.

The DS3803 also provides battery redundancy. In many applications data integrity is paramount. The
DS3803 provides two batteries for each SRAM and an internal isolation switch to select between them.
During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the
other automatically takes over. The switch between batteries is transparent to the user.

DS3803

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PIN DESCRIPTION Table 1

PIN SIGNAL

NAME

PIN

SIGNAL

NAME

PIN SIGNAL

NAME

PIN

SIGNAL

NAME

PIN

SIGNAL

NAME

D2B

D5C

D0A

D3B

D6C

CED

A10

D1A

D4B

D7C

OED

A11

D2A

D5B

WED

A12

D3A

D6B

CEC

GND

A13

D4A

D7B

OEC

A14

D5A

WEC

D6A

CEB

D0D

D7A

CEB

D1D

WEB

D2D

CEA

D0C

D3D

OEA

D1C

D4D

GND

WEA

D2C

D5D

D0B

D3C

D6D

D1B

D4C

D7D

DS3803

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

-0.3V to +7.0V

Operating Temperature

0ºC to 70ºC

Storage Temperature

-40ºC to +85ºC

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(

= 0ºC to 70ºC)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Power Supply Voltage

4.5

5.0

5.5

Logic 1 input Voltage

2.2

+0.3

Logic 0 input Voltage

-0.3

+0.8

DC ELECTRICAL CHARACTERISTICS

(

= 0ºC to 70ºC; V

= 5V ±10%)

PARAMETER

SYMBOL

TEST

CONDITION

MIN

TYP

MAX

UNITS

Input Leakage Current

0V V

-4

µA

Output Leakage Current

0V V

all

= V

-1

µA

Operating Current

CCO

min cycle,

duty=100% all

CE =

IL,

I/O

= 0,

IN =

or V

300

Standby Current

CCS

all

CE =

Output High Current

= 2.4V

-1.0

Output Low Current

= 0.4V

2.1

CAPACITANCE

= 25ºC)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

Output Capacitance

I/O

DS3803

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AC ELECTRICAL CHARACTERISTICS (

= 0ºC to 70ºC; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Read Cycle Time

Access Time

ACC

to Output Valid

to Output Active

COE

Deselection to Output High Z

Output Hold after Address
Change

Write Cycle Time

Write Pulse Width

Address Setup Time

Write Recovery Time

WR1

WR2

11
12

Active to Output High Z

ODW

Inactive to Output Active

OEW

Data Setup Time

Data Hold Time

DH1

DH2

11
12

TIMING DIAGRAM: READ CYCLE

DS3803

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TIMING DIAGRAM: POWER-DOWN AND POWER-UP

POWER-DOWN AND POWER-UP TIMING

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Fail Detect to

and

Inactive

1.5

µs

Slew from V

to 0V

300

µs

Slew from 0V to V

300

µs

Valid to

and

Inactive

Valid to End of Write

Protection

REC

125

= 25ºC)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Expected Data Retention
Time

years

WARNING

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.

NOTES:

is high throughout read cycle.

= V

or V

. If

= V

during write cycle, the output buffers remain in a high impedance

state.

DS3803

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is specified as the logical AND of

and

. t

is measured from the latter of

going low to the earlier of

going high.

is measured from the earlier of

going high.

These parameters are sampled with a 5 pF load and are not 100% tested.

If the

low transition occurs simultaneously with or later than the

low transition, the output

buffers remain in a high impedance state during this period.

If the

high transition occurs prior to or simultaneously with the

high transition, the output

buffers remain in a high impedance state during this period.

is low or the

low transition occurs prior to or simultaneously with the

low transition,

the output buffers remain in a high impedance state during this period.

Each DS3803 has a built-in switch that disconnects the lithium source until V

is first applied by the

user. The expected t

is defined as accumulative time in the absence of V

starting from the time

power is first applied by the user.

10.

In a power-down condition the voltage on any pin may not exceed the voltage on V

11.

WR1

, t

DH1

are measured from

going high.

12.

WR2

, t

DH2

are measured from

going high.

DC TEST CONDITIONS

Outputs Open
Cycle = 200 ns
All Voltages are Referenced to Ground

AC TEST CONDITIONS

Output Load: 100 pF + 1TTL gate
Input Pulse Levels: 0 - 3.0 V
Timing Measurements Reference Levels:

Input - 1.5V
Output - 1.5V

Input Pulse Rise and Fall Times: 5 ns

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