1 of 26

052302

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here:

http://www.maxim-ic.com/errata

FEATURES

§ 8051-compatible microprocessor adapts to its

task
Accesses up to 128kB of nonvolatile

SRAM

In-system programming through on-chip

serial port

Can modify its own program or data

memory

Accesses memory on a separate byte-wide

bus

Performs CRC-16 check of NV RAM

memory

Decodes memory and peripheral chip

enables

§ High-reliability operation

Maintains all nonvolatile resources for

over 10 years

Power-fail reset
Early warning power-fail interrupt
Watchdog timer
Lithium backs user SRAM for

program/data storage

Precision bandgap reference for power

monitor

§ Fully 8051-compatible

128kB scratchpad RAM
Two timer/counters
On-chip serial port
32 parallel I/O port pins

§ Software security available with DS5002FP

secure microprocessor

PIN ASSIGNMENT (Top View)

P0.4AD4

CE2

PE2
BA9

P0.3/AD3

BA8

P0.2/AD2

BA13

P0.1/AD1

R/W

P0.0/AD0

VCC0

VCC

MSEL

P1.0

BA14

P1.1

BA12

P1.2

BA7

P1.3

PE3
PE4
BA6

P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
BA15
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0

DS5001FP

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

P1.4

BA5

P1.5

BA4

P1.6

BA3

P1.7

PROG

BA2

RST

BA1

P3.0/RXD

BA0

P3.1/TXD

P3.2/INT0

P3.3/INT1

BA11

P0.5/AD5

PE1

P0.6/AD6

BA10

P0.7/AD7

CE1

CE1N

BD7

BD6

PSEN

BD5

P2.7/A15

BD4

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

DS5001FP

128k Soft Microprocessor Chip

www.maxim-ic.com

80-Pin MQFP

44-Pin MQFP

DS5001FP

2 of 26

DESCRIPTION

The DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM
technology and designed for systems that need large quantities of nonvolatile memory. It provides full
compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM
instead of ROM, the user can program and then reprogram the microprocessor while in-system. The
application software can even change its own operation, which allows frequent software upgrades,
adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for
data logging applications. It also connects easily to a Dallas real-time clock.

The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a nonmultiplexed
byte-wide address and data bus for memory access. This bus performs all memory access and provides
decoded chip enables for SRAM, which leaves the 32 I/O port pins free for application use. The
DS5001FP uses ordinary SRAM and battery-backs the memory contents for over 10 years at room
temperature with a small external battery. A DS5001FP also provides high-reliability operation in harsh
environments. These features include the ability to save the operating state, power-fail reset, power-fail
interrupt, and watchdog timer.

A user programs the DS5001FP through its on-chip serial bootstrap loader. The bootstrap loader
supervises the loading of software into NV RAM, validates it, and then becomes transparent to the user.
Software can be stored in multiple 32kB or one 128kB CMOS SRAM(s). Using its internal partitioning,
the DS5001FP can divide a common RAM into user-selectable program and data segments. This partition
can be selected at program loading time, but can then be modified later at any time. The microprocessor
decodes memory access to the SRAM and addresses memory through its byte-wide bus. Memory portions
designated code or ROM are automatically write-protected by the microprocessor. Combining program
and data storage in one device saves board space and cost.

The DS5001FP offers several bank switches for access to even more memory. In addition to the primary
data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip
enables. This area can be used for memory-mapped peripherals or more data storage. The DS5001FP can
also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kB of data space.
Lastly, the DS5001FP provides one additional bank switch that changes up to 60kB of the NV RAM
program space into data memory. Thus, with a small amount of logic, the DS5001 accesses up to 252kB
of data memory.

The DS2251T is available (Refer to the data sheet at

www.maxim-ic.com/microcontrollers

.) for users

who want a preconstructed module using the DS5001FP, RAM, lithium cell, and a real-time clock. For
more details, refer to the Secure Microcontroller User's Guide. For users desiring software security, the
DS5002FP is functionally identical to the DS5001FP but provides superior firmware security. The 44-pin
version of the device is functionally identical to the 80-pin version but sports a reduced pin count and
footprint.

Refer to the Secure Microcontroller User's Guide for operating details. This data sheet provides ordering
information, pinout, and electrical specifications.

ORDERING INFORMATION

PART

PIN-PACKAGE

MAX. CLOCK SPEED (MHz)

TEMP. RANGE (°C)

DS5001FP-16

80-MQFP

0 to +70

DS5001FP-16N

80-MQFP

-40 to +85

DS5001FP-12-44

44-MQFP

0 to +70

DS5001FP

4 of 26

PIN DESCRIPTION

80-PIN

MQFP

44-PIN

MQFP

SIGNAL

DESCRIPTION

11, 9, 7,
5, 1, 79,

77, 75

(P0.5)

P0.0P0.7

General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.

15, 17,
19, 21,
25, 27,

29, 31

(P1.3)

P1.0P1.7

General-Purpose I/O Port 1

49, 50,
51, 56,
58, 60,

64, 66

N/A

P2.0P2.7

General-Purpose I/O Port 2. Also serves as the MSB of the address in expanded memory
accesses, and as pins of the RPC mode when used.

P3.0 RXD

General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on board
UART. This pin should not be connected directly to a PC COM port.

P3.1 TXD

General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on board
UART. This pin should not be connected directly to a PC COM port.

N/A

P3.2

INT0

General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.

P3.3

INT1

General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.

N/A

P3.4 T0

General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.

P3.5 T1

General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.

P3.6

General-Purpose I/O Port Pin. Also serves as the write strobe for expanded bus
operation.

N/A

P3.7

General-Purpose I/O Port Pin. Also serves as the read strobe for expanded bus operation.

PSEN

Program Store Enable. This active-low signal is used to enable an external program
memory when using the expanded bus. It is normally an output and should be unconnected
if not used.

PSEN

also is used to invoke the bootstrap loader. At this time,

PSEN

is pulled

down externally. This should only be done once the DS5001FP is already in a reset state.
The device that pulls down should be open drain since it must not interfere with

PSEN

under normal operation.

RST

Active-High Reset Input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally so this pin can be left unconnected if not used. An RC power-on
reset circuit is not needed and is not recommended.

ALE

Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus
on port 0. This pin is normally connected to the clock input on a '373 type transparent
latch.

47, 48

14, 15

XTAL2,

XTAL1

XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.

GND

Logic Ground

VCC

- +5V

VCCO

CCO

- V

Output. This is switched between V

and V

by internal circuits based on the

level of V

. When power is above the lithium input, power will be drawn from V

. The

lithium cell remains isolated from a load. When V

is below V

, the V

CCO

switches to the

source. V

CCO

should be connected to the V

pin of an SRAM.

VLI

Lithium Voltage Input. Connect to a lithium cell greater than V

LIMIN

and no greater than

LImax

as shown in the electrical specifications. Nominal value is +3V.

53, 16,

8, 18,

80, 76,

4, 6, 20,

24, 26,
28, 30,

41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,

BA140

Byte-Wide Address-Bus Bits 140. This bus is combined with the nonmultiplexed data
bus (BD70) to access NV SRAM. Decoding is performed using

CE1

through

CE4

Therefore, BA15 is not actually needed. Read/write access is controlled by R/

. BA140

connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are
unconnected. If a 128k SRAM is used, the micro converts

CE2

and

CE3

to serve as A16

DS5001FP

5 of 26

33, 35,

and A15 respectively.

71, 69,
67, 65,
61, 59,

57, 55

28, 26,
24, 23,
21, 20,

19, 18

BD70

Byte-Wide Data-Bus Bits 70. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA140) to access NV SRAM. Decoding is performed on

CE1

and

CE2

. Read/write access is controlled by R/

. BD70 connect directly to an

SRAM, and optionally to a real-time clock or other peripheral.

Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.

CE1

Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-
wide bus. It connects to the chip enable input of one SRAM.

CE1

is lithium-backed. It

remains in a logic high inactive state when V

falls below V

N/A

CE1N

Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.

CE2

Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts

CE2

into A16 for a 128k x 8 SRAM.

CE2

is lithium-backed and remains at a logic high when

falls below V

CE3

Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts

CE3

into A15 for a 128k x 8 SRAM.

CE3

is lithium-backed and remains at a logic high when

falls below V

N/A

CE4

Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.

CE4

is lithium-backed and remains at a logic high when V

< V

N/A

PE1

Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283.

PE1

is lithium-backed and remains at a logic high when V

falls

below V

. Connect

PE1

to battery-backed functions only.

N/A

PE2

Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when
the PES bit is set to a logic 1.

PE2

is lithium-backed and remains at a logic high when V

falls below V

. Connect

PE2

to battery-backed functions only.

N/A

PE3

Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1.

PE3

is not lithium-backed and can be connected to any type

of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V

< V

N/A

PE4

Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1.

PE4

is not lithium-backed and can be connected to any type

of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V

< V

N/A

PROG

Invokes the bootstrap loader on a falling edge. This signal should be debounced so that
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.

N/A

VRST

This I/O pin (open drain with internal pullup) indicates that the power supply (V

)

has fallen below the V

CCmin

level and the micro is in a reset state. When this occurs, the

DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when V

= 0V. Because it is an I/O pin, it also forces a reset if pulled

low externally. This allows multiple parts to synchronize their power-down resets.

N/A

This output goes to a logic 0 to indicate that V

< V

and the micro has switched to

lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
V

= 0V. The normal application of this signal is to control lithium powered current to

isolate battery-backed functions from non-battery-backed functions.

MSEL

Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.

No Connect.

DS5001FP

6 of 26

INSTRUCTION SET

The DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction
set and operation are provided in the Secure Microcontroller User's Guide. Also note that the DS5001FP
is embodied in the DS2251T module. The DS2251T combines the DS5001FP with between 32k and 128k
of SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module.

MEMORY ORGANIZATION

Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of
data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The
user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program
range and data range. Any area not mapped into the NV RAM is reached by the expanded bus on ports 0
and 2. An alternate configuration allows dynamic partitioning of a 64k space as shown in Figure 3.
Selecting PES=1 provides another 64k of potential data storage or memory-mapped peripheral space as
shown in Figure 4. These selections are made using special function registers. The memory map and its
controls are covered in detail in the Secure Microcontroller User's Guide.

Figure 2. MEMORY MAP IN NONPARTITIONABLE MODE (PM = 1)

DS5001FP

10 of 26

Figure 6. DS5001FP CONNECTION TO 64k x 8 SRAM

POWER MANAGEMENT

The DS5001FP monitors V

to provide power-fail reset, early warning power-fail interrupt, and switch

over to lithium backup. It uses an internal bandgap reference in determining the switch points. These are
called V

PFW

, V

CCMIN

, and V

, respectively. When V

drops below V

PFW

, the DS5001FP performs an

interrupt vector to location 2Bh if the power-fail warning was enabled. Full processor operation continues
regardless. When power falls further to V

CCMIN

, the DS5001FP invokes a reset state. No further code

execution is performed unless power rises back above V

CCMIN

. All decoded chip enables and the R/

signal go to an inactive (logic 1) state. V

is still the power source at this time. When V

drops further

to below V

, internal circuitry switches to the lithium cell for power. The majority of internal circuits are

disabled and the remaining nonvolatile states are retained. Any devices connected V

CCO

are powered by

the lithium cell at this time. V

CCO

is at the lithium battery voltage minus approximately 0.45V. This drop

varies depending on the load. Low power SRAMs should be used for this reason. When using the
DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the
desired backup lifetime. Note that the lithium cell is only loaded when V

< V

. The User's Guide has

more information on this topic. The trip points V

CCMIN

and V

PFW

are listed in Electrical Specifications.

DS5001FP

11 of 26

ABSOLUTE MAXIMUM RATINGS*

Voltage Range on Any Pin Relative to Ground

-0.3V to (V

+ 0.5V)

Voltage Range on V

Related to Ground

-0.3

°C to 6.0°C

Operating Temperature Range

-40

°C to +85°C

Storage Temperature Range

-55

°C to +125°C

Soldering Temperature

See IPC/JEDEC J-STD-020A

This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

Storage temperature is defined as the temperature of the device when V

= 0V and V

= 0V. In this

state, the contents of SRAM are not battery-backed and are undefined.

DC CHARACTERISTICS (T

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Low Voltage

-0.3

+0.8

Input High Voltage

IH1

2.0

+ 0.3

Input High Voltage
(RST, XTAL1,

PROG

)

IH2

3.5

+ 0.3

Output Low Voltage
at I

= 1.6mA (Ports 1, 2, 3,

)

OL1

0.15

0.45

1, 11

Output Low Voltage
at I

= 3.2mA (Ports 0, ALE,

PSEN

BA150, BD70, R/

CE1N

14,

14, V

RST

)

OL2

0.15

0.45

Output High Voltage
at I

= -80µA (Ports 1, 2, 3)

OH1

2.4

4.8

Output High Voltage
at I

= -400µA (Ports 0, ALE,

PSEN

PF ,

BA150, BD70, R/

CE1N

14,

14, V

RST

)

OH2

2.4

4.8

Input Low Current
V

= 0.45V (Ports 1, 2, 3)

-50

µA

Transition Current; 1 to 0
V

= 2.0V (Ports 1, 2, 3)

(0°C to +70°C)

-500

µA

Transition Current; 1 to 0
V

= 2.0V (Ports 1, 2, 3)

(-40°C to +85°C)

-600

µA

DS5001FP

12 of 26

DC CHARACTERISTICS (continued) (T

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Leakage Current
0.45 < V

< V

(Port 0, MSEL)

+10

µA

RST Pulldown Resistor
(0°C to +70°C)

150

RST Pulldown Resistor
(-40°C to +85°C)

180

VRST

Pullup Resistor

4.7

PROG

Pullup Resistor

Power-Fail Warning Voltage
(0°C to +70°C)

PFW

4.25

4.37

4.50

Power-Fail Warning Voltage
(-40°C to +85°C)

PFW

4.1

4.37

4.6

1, 10

Minimum Operating Voltage
(0°C to +70°C)

CCMIN

4.00

4.12

4.25

Minimum Operating Voltage
(-40°C to +85°C)

CCMIN

3.85

4.09

4.25

1, 10

Lithium Supply Voltage

2.5

4.0

Operating Current at 16MHz

Idle Mode Current at 12MHz
(0°C to +70°C)

IDLE

7.0

Idle Mode Current at 12MHz
(-40°C to +85°C)

IDLE

8.0

3, 10

Stop Mode Current

STOP

µA

Pin Capacitance

Output Supply Voltage (V

CCO

)

CCO1

-0.45

1, 2

Output Supply Battery-Backed Mode
(V

CCO

1-4,

1-2)

(0°C to +70°C)

CCO2

-0.65

1, 8

Output Supply Battery-Backed Mode
(V

CCO

1-4,

1-2)

(-40°C to +85°C)

CCO2

-0.9

1, 8, 10

Output Supply Current
at V

CCO

= V

- 0.45V

CCO1

Lithium-Backed Quiescent Current
(0°C to +70°C)

Lithium-Backed Quiescent Current
(-40°C to +85°C)

500

Reset Trip Point in Stop Mode
With BAT = 3.0V (0°C to +70°C)
With BAT = 3.0V (-40°C to +85°C)
With BAT = 3.0V (0°C to +70°C)

4.0

3.85

4.4

4.25
4.25
4.65

1, 10

DS5001FP

13 of 26

AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(T

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

MAX

UNITS

Oscillator Frequency

1/ t

CLK

1.0

MHz

ALE Pulse Width

ALPW

CLK

- 40

Address Valid to ALE Low

AVALL

CLK

- 40

Address Hold After ALE Low

AVAAV

CLK

- 35

ALE Low to Valid Instruction In
at 12MHz

at 16MHz

ALLVI

CLK

- 150

CLK

- 90

ns
ns

ALE Low to

PSEN

Low

ALLPSL

CLK

- 25

PSEN

Pulse Width

PSPW

CLK

- 35

PSEN

Low to Valid Instruction In

at 12MHz

at 16MHz

PSLVI

CLK

- 150

CLK

- 90

ns
ns

Input Instruction Hold After

PSEN

Going

High

PSIV

Input Instruction Float After

PSEN

Going

High

PSIX

CLK

- 20

Address Hold After

PSEN

Going High

PSAV

CLK

- 8

Address Valid to Valid Instruction In
at 12MHz

at 16MHz

AVVI

CLK

- 150

CLK

- 90

ns
ns

PSEN

Low to Address Float

PSLAZ

Pulse Width

RDPW

CLK

- 100

Pulse Width

WRPW

CLK

- 100

Low to Valid Data In

at 12MHz
at 16MHz

RDLDV

CLK

- 165

CLK

- 105

ns
ns

Data Hold After

High

RDHDV

Data Float After

High

RDHDZ

CLK

- 70

ALE Low to Valid Data In at 12MHz

at 16MHz

ALLVD

CLK

- 150

CLK

- 90

Valid Address to Valid Data In at 12MHz

at 16MHz

AVDV

CLK

- 165

CLK

- 105

ALE Low to

Low

ALLRDL

CLK

- 50

CLK

+ 50

Address Valid to

Low

AVRDL

CLK

- 130

Data Valid to

Going Low

DVWRL

CLK

- 60

Data Valid to

High

at 12MHz
at 16MHz

DVWRH

CLK

- 150

CLK

- 90

Data Valid After

High

WRHDV

CLK

- 50

Low to Address Float

RDLAZ

High to ALE High

RDHALH

CLK

- 40

CLK

+ 50

DS5001FP

19 of 26

AC CHARACTERISTICS (continued)
BYTE-WIDE ADDRESS/DATA BUS TIMING
(T

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

MAX

UNITS

Delay to Byte-Wide Address Valid from

CE1

CE2

, or

CE1N

Low During Op Code

Fetch

CE1LPA

Pulse Width of

1-4,

1-4 or

CE1N

CEPW

CLK

- 35

Byte-Wide Address Hold After

CE1

CE2

, or

CE1N

High During Op Code Fetch

CE1HPA

CLK

- 20

Byte-Wide Data Setup to

CE1

CE2

, or

CE1N

High During Op Code Fetch

OVCE1H

CLK

+ 40

Byte-Wide Data Hold After

CE1

CE2

CE1N

High During Op Code Fetch

CE1HOV

Byte-Wide Address Hold After

1-4,

1-4, or

CE1N

High During MOVX

CEHDA

CLK

- 30

Delay from Byte-Wide Address Valid

1-4,

1-4, or

CE1N

Low During MOVX

CELDA

CLK

- 35

Byte-Wide Data Setup to

1-4,

1-4, or

CE1N

High During MOVX (read)

DACEH

CLK

+ 40

Byte-Wide Data Hold After

1-4,

1-4, or

CE1N

High During MOVX (read)

CEHDV

Byte-Wide Address Valid to R/

Active

During MOVX (write)

AVRWL

CLK

- 35

Delay from R/

Low to Valid Data Out

During MOVX (write)

RWLDV

Valid Data-Out Hold Time from

1-4,

1-4, or

CE1N

High

CEHDV

CLK

- 15

Valid Data-Out Hold Time from R/

High

RWHDV

Write Pulse Width (R/

Low Time)

RWLPW

CLK

- 20

DS5001FP

21 of 26

RPC AC CHARACTERISTICS, DBB WRITE (T

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

MAX

UNITS

, A

Setup to

61A

, Hold After

61B

, Hold After

Pulse Width

160

Data Setup to

130

Data Hold After

AC CHARACTERISTICS, DMA (T

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

MAX

UNITS

DACK

ACC

DACK

CAC

DACK

to Data Valid

ACD

130

to DRQ Cleared

CRQ

110

AC CHARACTERISTICS,

PROG

= 0°C to +70°C; V

= 5V ±10%)

PARAMETER

SYMBOL

MIN

MAX

UNITS

PROG

Low to Active

PRA

CLKS

PROG

High to Inactive

PRI

CLKS

DS5001FP

23 of 26

NOTES:

All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1) All voltages are referenced to ground.
2) Maximum operating I

is measured with all output pins disconnected; XTAL1 driven with t

CLKR

CLKF

= 10ns, V

= 0.5V; XTAL2 disconnected; RST = PORT0 = V

, MSEL = V

3) Idle mode, I

IDLE

, is measured with all output pins disconnected; XTAL1 driven with t

CLKR

CLKF

= 10ns, V

= 0.5V; XTAL2 disconnected; PORT0 = V

, RST = MSEL = V

4) Stop mode, I

STOP

, is measured with all output pins disconnected; PORT0 = V

; XTAL2 not

connected; RST = MSEL = XTAL1 = V

5) Pin capacitance is measured with a test frequency: 1MHz, T

= +25°C.

6) I

CCO1

is the maximum average operating current that can be drawn from V

CCO

in normal operation.

7) I

is the current drawn from V

input when V

= 0V and V

CCO

is disconnected.

8) V

CCO2

is measured with V

< V

, and a maximum load of 10µA on V

CCO

9) Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the

time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for a worst-case specification on this time.

10) This parameter applies to industrial temperature operation.
11)

pin operation is specified with V

BAT

³ 3.0V.

DS5001FP

26 of 26

REVISION HISTORY

The following represent the key differences between 112795 and 073096 version of the DS5001FP data
sheet. Please review this summary carefully.

1) Change V

CC02

specification from V

- 0.5 to V

- 0.65 (PCN F62501).

2) Update mechanical specifications.

The following represent the key differences between 073096 and 111996 version of the DS5001FP data
sheet. Please review this summary carefully.

1) Change V

CC01

from V

- 0.3 to V

- 0.35.

The following represent the key differences between 111996 and 061297 version of the DS5001FP data
sheet. Please review this summary carefully.

signal moved from V

OL2

test specification to V

OL1

. PCN No. (D72502)

2) AC characteristics for battery-backed SDI pulse specification added.

The following represent the key differences between 061297 and 051099 version of the DS5001FP data
sheet. Please review this summary carefully.

1) Reduced absolute maximum voltage to V

+ 0.5V.

2) Added note clarifying storage temperature specification is for non-battery-backed state.
3) Changed R

min (industrial temp range) from 40k

W to 30kW.

4) Changed V

PFW

max (industrial temp range) from 4.5V to 4.6V.

5) Added industrial specification for I

6) Reduced t

CE1HOV

and t

CEHDV

from 10ns to 0ns.

The following represent the key differences between 051099 and 052499 version of the DS5001FP data
sheet. Please review this summary carefully.

1) Minor markups and ready for approval.

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