3D7314
MONOLITHIC QUADRUPLE
FIXED DELAY LINE
(SERIES 3D7314)
FEATURES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range: 10 through 500ns
Delay tolerance: 2% or 1.0ns
Temperature stability: 1% typical (0C-70C)
Vdd stability: 1% typical (4.75V-5.25V)
Minimum input pulse width: 20% of total delay
Static Idd: 1.3ma typical
Minimum input pulse width: 25% of total delay
FUNCTIONAL DESCRIPTION
The 3D7314 Quadruple Delay Line product family consists of fixed-
delay CMOS integrated circuits. Each package contains four matched,
independent delay lines. Delay values can range from 10ns through
500ns. The input is reproduced at the output without inversion, shifted
in time as per the user-specified dash number. The 3D7314 is TTL-
and CMOS-compatible, capable of driving ten 74LS-type loads, and
features both rising- and falling-edge accuracy.
The all-CMOS 3D7314 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and a space saving
surface mount 14-pin SOIC.
PACKAGES
14
13
12
11
10
9
8
1
2
3
4
5
6
7
I1
N/C
I2
I3
I4
N/C
GND
VDD
N/C
O1
N/C
O2
O3
O4
3D7314-xx DIP
3D7314G-xx Gull-Wing
1
2
3
4
5
6
7
14
13
12
11
10
9
8
I1
N/C
I2
I3
I4
N/C
GND
VDD
N/C
O1
N/C
O2
O3
O4
3D7314D-xx
SOIC
(150 Mil)
PIN DESCRIPTIONS
I1
Delay Line 1 Input
I2
Delay Line 2 Input
I3
Delay Line 3 Input
I4
Delay Line 4 Input
O1
Delay Line 1 Output
O2
Delay Line 2 Output
O3
Delay Line 3 Output
O4
Delay Line 4 Output
VDD +5
Volts
GND Ground
N/C No
Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DELAY
INPUT RESTRICTIONS
DIP-14
3D7314
DIP-14
3D7314G
SOIC-14
3D7314D
PER LINE
(ns)
Max Operating
Frequency
Absolute Max
Oper. Freq.
Min Operating
Pulse Width
Absolute Min
Oper. P.W.
-10 -10 -10 10
1.0
33.3 MHz
100.0 MHz
15.0 ns
5.0 ns
-15 -15 -15 15
1.0
22.2 MHz
100.0 MHz
22.5 ns
5.0 ns
-20 -20 -20 20
1.0
16.7 MHz
100.0 MHz
30.0 ns
5.0 ns
-25 -25 -25 25
1.0
13.3 MHz
83.3 MHz
37.5 ns
6.0 ns
-30 -30 -30 30
1.0
11.1 MHz
71.4 MHz
45.0 ns
7.0 ns
-40 -40 -40 40
1.0
8.33 MHz
62.5 MHz
60.0 ns
8.0 ns
-50 -50 -50 50
1.0
6.67 MHz
50.0 MHz
75.0 ns
10.0 ns
-100 -100 -100 100
2.0
3.33 MHz
25.0 MHz
150.0 ns
20.0 ns
-200 -200 -200 200
4.0
1.67 MHz
12.5 MHz
300.0 ns
40.0 ns
-300 -300 -300 300
6.0
1.11 MHz
8.33 MHz
450.0 ns
60.0 ns
-400 -400 -400 400
8.0
0.83 MHz
6.25 MHz
600.0 ns
80.0 ns
-500 -500 -500
500
10.0
0.67 MHz
5.00 MHz
750.0 ns
100.0 ns
NOTES: Any delay between 10 and 500 ns not shown is also available.
2003 Data Delay Devices
For mechanical dimensions, click
here
.
For package marking details, click
here
.
Doc #03005
DATA DELAY DEVICES, INC.
1
12/8/03
3 Mt. Prospect Ave. Clifton, NJ 07013
3D7314
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7314 quadruple delay line architecture is
shown in Figure 1. The individual delay lines are
composed of a number of delay cells connected
in series. Each delay line produces at its output
a replica of the signal present at its input, shifted
in time. The delay lines are matched and share
the same compensation signals, which minimizes
line-to-line delay deviations over temperature and
supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7314 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7314 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
O1
I1
O2
I2
O3
I3
O4
I4
Temp & VDD
Compensation
VDD
GND
Figure 1: 3D7314 Functional Diagram
Delay
Line
Delay
Line
Delay
Line
Delay
Line
Doc #03005
DATA DELAY DEVICES, INC.
2
12/8/03
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7314
Doc #03005
DATA DELAY DEVICES, INC.
3
12/8/03
3 Mt. Prospect Ave. Clifton, NJ 07013
APPLICATION NOTES (CONT'D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7304 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 200
PPM/C, which is equivalent to a variation , over
the 0C-70C operating range, of
1% from the
room-temperature delay settings and/or 0.5ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to
1% of the delay settings at
the nominal 5.0VDC power supply and/or 1.0ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL
MIN MAX
UNITS
NOTES
DC Supply Voltage
V
DD
-0.3 7.0 V
Input Pin Voltage
V
IN
-0.3
V
DD
+0.3 V
Input Pin Current
I
IN
-1.0
1.0
mA
25C
Storage Temperature
T
STRG
-55 150 C
Lead Temperature
T
LEAD
300
C
10
sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN TYP MAX
UNITS NOTES
Static Supply Current*
I
DD
1.3
2.0
mA
V
DD
= 3.6V
High Level Input Voltage
V
IH
2.0 V
Low Level Input Voltage
V
IL
0.8
V
High Level Input Current
I
IH
-0.1
0.0
0.1
A
V
IH
= V
DD
Low Level Input Current
I
IL
-0.1
0.0
0.1
A
V
IL
= 0V
High Level Output Current
I
OH
-8.0
-6.0
mA
V
DD
= 4.75V
V
OH
= 2.4V
Low Level Output Current
I
OL
6.0
7.5 mA
V
DD
= 4.75V
V
OL
= 0.4V
Output Rise & Fall Time
T
R
& T
F
2 ns
C
LD
= 5 pf
*I
DD
(Dynamic) = 4 * C
LD
* V
DD
* F
Input Capacitance = 10 pf typical
where: C
LD
= Average capacitance load/line (pf)
Output Load Capacitance (C
LD
) = 25 pf max
F = Input frequency (GHz)
3D7314
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25
o
C
3
o
C
R
load
: 10K
10%
Supply Voltage (Vcc): 5.0V
0.1V
C
load
: 5pf
10%
Input Pulse:
High = 3.0V
0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V
0.1V
Source Impedance: 50
Max.
10K
470
5pf
Device
Under
Test
Digital
Scope
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width: PW
IN
= 1.25 x Total Delay
Period: PER
IN
= 2.5 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUT1
OUT2
OUT4
OUT3
OUT
TRIG
IN
REF
TRIG
Figure 2: Test Setup
DEVICE UNDER
TEST (DUT)
DIGITAL SCOPE/
TIME INTERVAL COUNTER
PULSE
GENERATOR
IN4
COMPUTER
SYSTEM
PRINTER
IN3
IN2
IN1
Figure 3: Timing Diagram
t
PLH
t
PHL
PER
IN
PW
IN
t
RISE
t
FALL
0.6V
0.6V
1.5V
1.5V
2.4V
2.4V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #03005
DATA DELAY DEVICES, INC.
4
12/8/03
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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