3D7501
Doc #96010
DATA DELAY DEVICES, INC.
1
5/19/97
3 Mt. Prospect Ave. Clifton, NJ 07013
MONOLITHIC MANCHESTER
ENCODER
(SERIES 3D7501)
FEATURES
All-silicon, low-power CMOS
technology
TTL/CMOS compatible inputs and
outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
FUNCTIONAL DESCRIPTION
The 3D7501 is a monolithic CMOS Manchester Encoder. The clock
and data, present at the unit input, are combined into a single bi-
phase-level signal. In this encoding mode, a logic one is represented
by a high-to-low transition within the bit cell, while a logic zero is
represented by a low-to-high transition. The unit operating baud rate (in
Mbaud) is equal to the input clock frequency (in MHZ) . All pins
marked N/C must be left unconnected.
The all-CMOS 3D7501 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL Manchester Encoder. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is
offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-
pin SOICs.
data
delay
devices,
inc.
3
PACKAGES
8
7
6
5
1
2
3
4
CLK
RESB
DAT
GND
VDD
N/C
TXB
TX
3D7501M
DIP (.300)
3D7501H
Gull Wing (.300)
3D7501Z
SOIC (.150)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
CLK
N/C
N/C
RESB
DAT
N/C
GND
VDD
N/C
N/C
N/C
N/C
TXB
TX
3D7501
DIP (.300)
3D7501G Gull Wing (.300)
3D7501D SOIC (.150)
PIN DESCRIPTIONS
DAT
Data Input
CLK
Clock Input
RESB Reset
TX
Signal Output
TXB
Inverted Signal Output
VCC
+5 Volts
GND
Ground
3D7501
Doc #96010
DATA DELAY DEVICES, INC.
2
5/19/97
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
The 3D7501 Manchester Encoder samples the
data input at the rising edge of the input clock.
The sampled data is used in conjunction with the
clock rising and falling edges to generate the by-
phase level Manchester code.
INPUT SIGNAL CHARACTERISTICS
The 3D7501 Manchester Encoder inputs
are
TTL compatible. The user should assure
himself that the 1.5 volt TTL threshold is used
when referring to all timing, especially to the
input clock duty cycle.
CLOCK DUTY CYCLE ERRORS
The 3D7501 Manchester Encoder employs the
timing of the clock rising and falling edges (duty
cycle) to implement the required coding scheme.
To reduce the difference between the output data
high time and low time, it is essential that the
deviation of the input clock duty cycle from 50/50
be minimized.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7501 presents at its outputs the true and
the complimented encoded data.
The High-to-Low time skew of the selected data
output should be budgeted by the user, as it
relates to his application, to satisfactorily
estimate the distortion of the transmitted data
stream.
Such estimate is very useful in determining the
functionality and margins of the data link, if a
3D7502 Manchester Decoder is used to decode
the received data.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D7501 Manchester encoder utilizes
novel and innovative compensation circuitry to
minimize timing variations induced by
fluctuations in power supply and/or temperature.
RESET
(RESB)
CLOCK
(CIN)
DATA
(DIN)
TRANSMIT
(TX)
TRANSMIT
(TXB)
t
DS
t
DH
Figure 1: Timing Diagram
1/f
C
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
Power-on reset (Left high for normal operation)
T
2H
T
2L
T
1H
T
1L
3D7501
Doc #96010
DATA DELAY DEVICES, INC.
3
5/19/97
3 Mt. Prospect Ave. Clifton, NJ 07013
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DC Supply Voltage
V
DD
-0.3
7.0
V
Input Pin Voltage
V
IN
-0.3
V
DD
+0.3
V
Input Pin Current
I
IN
-10
10
mA
25C
Storage Temperature
T
STRG
-55
150
C
Lead Temperature
T
LEAD
300
C
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Static Supply Current*
I
DD
40
mA
High Level Input Voltage
V
IH
2.0
V
Low Level Input Voltage
V
IL
0.8
V
High Level Input Current
I
IH
1.0
A
V
IH
= V
DD
Low Level Input Current
I
IL
1.0
A
V
IL
= 0V
High Level Output Current
I
OH
-4.0
mA
V
DD
= 4.75V
V
OH
= 2.4V
Low Level Output Current
I
OL
4.0
mA
V
DD
= 4.75V
V
OL
= 0.4V
Output Rise & Fall Time
T
R
& T
F
2
ns
C
LD
= 5 pf
*I
DD
(Dynamic) = 2 * C
LD
* V
DD
* F
Input Capacitance = 10 pf typical
where:
C
LD
= Average capacitance load/pin (pf)
Output Load Capacitance (C
LD
) = 25 pf max
F = Input frequency (GHz)
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Baud Rate
f
BN
50
MBaud
Clock Frequency
f
C
50
MHz
Data set-up to clock rising
t
DS
3.5
ns
Data hold from clock rising
t
DH
0
ns
TX High-Low time skew
t
1H
- t
1L
-3.5
3.5
ns
1
TXB High-Low time skew
t
2H
- t
2L
-2.0
2.0
ns
1
TX - TXB High/Low time skew
t
1H
- t
2L
-3.0
3.0
ns
1
Notes: 1: Assumes a 50% duty cycle clock input
3D7501
Doc #96010
DATA DELAY DEVICES, INC.
4
5/19/97
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25
o
C
3
o
C
R
load
:
10K
10%
Supply Voltage (Vcc): 5.0V
0.1V
C
load
:
5pf
10%
Input Pulse:
High = 3.0V
0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V
0.1V
Source Impedance:
50
Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PW
IN
= 1/(2*BAUD)
Period:
PER
IN
= 1/BAUD
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
10K
470
5pf
Device
Under
Test
Digital
Scope
OUT
TRIG
IN
TRIG
Figure 2: Test Setup
DEVICE UNDER
TEST (DUT)
DIGITAL SCOPE
WAVEFORM
GENERATOR
OUT
IN
COMPUTER
SYSTEM
PRINTER
Figure 3: Timing Diagram
t
PLH
t
PHL
PER
IN
PW
IN
t
RISE
t
FALL
0.6V
0.6V
1.5V
1.5V
2.4V
2.4V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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