DDU8C3
Doc #00115
DATA DELAY DEVICES, INC.
1
5/19/00
3 Mt. Prospect Ave. Clifton, NJ 07013
5-TAP, 3.3V CMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C3)
FEATURES
PACKAGES
Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
10 T
2
L fan-out capability
FUNCTIONAL DESCRIPTION
The DDU8C3-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). For dash
numbers 5020 and above, the total delay of the line is measured from IN to
T5, and the nominal tap-to-tap delay increment is given by one-fifth of the
total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay
increment is given by one-fourth of the total delay.
SERIES SPECIFICATIONS
Minimum input pulse width: 40% of total delay
Output rise time: 2ns typical
Supply voltage: 3.3VDC
0.3V
Supply current:
I
CCL
= 40
a typical
I
CCH
= 7ma typical
Operating temperature: -40
to 85
C
Temp. coefficient of total delay: 300 PPM/
C
25%
25%
25%
25%
VDD
GND
IN
T1
T2
T3
T4
T5
Functional diagram for dash numbers < 5020
3.0ns
20%
20%
20%
20%
20%
VDD
GND
IN
T1
T2
T3
T4
T5
Functional diagram for dash numbers >= 5020
2000 Data Delay Devices
data
delay
devices,
inc.
3
8
7
6
5
1
2
3
4
IN
T2
T4
GND
VDD
T1
T3
T5
DDU8C3-xx
DIP
DDU8C3-xxA1 Gull-Wing
PIN DESCRIPTIONS
IN
Signal Input
T1-T5 Tap Outputs
VDD
+3.3 Volts
GND
Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Total
Delay (ns)
Delay Per
Tap (ns)
DDU8C3-5004
4
1.0 *
1.0
0.5
DDU8C3-5006
6
1.0 *
1.5
0.5
DDU8C3-5008
8
2.0 *
2.0
1.0
DDU8C3-5010
10
2.0 *
2.5
1.0
DDU8C3-5012
12
2.0 *
3.0
1.0
DDU8C3-5014
14
2.0 *
3.5
1.0
DDU8C3-5020
20
2.0
4.0
1.0
DDU8C3-5025
25
2.0
5.0
1.5
DDU8C3-5030
30
2.0
6.0
1.5
DDU8C3-5035
35
2.0
7.0
1.8
DDU8C3-5040
40
2.0
8.0
2.0
DDU8C3-5045
45
2.25
9.0
2.0
DDU8C3-5050
50
2.5
10.0
2.0
DDU8C3-5060
60
3.0
12.0
2.0
DDU8C3-5075
75
3.75
15.0
2.5
DDU8C3-5100
100
5.0
20.0
3.0
DDU8C3-5125
125
6.5
25.0
3.0
DDU8C3-5150
150
7.5
30.0
3.0
DDU8C3-5175
175
8.0
35.0
4.0
DDU8C3-5200
200
10.0
40.0
4.0
DDU8C3-5250
250
12.5
50.0
5.0
* Total delay is referenced to first tap output
Input to first tap = 3.0ns
1ns
NOTE: Any dash number between 5004 and 5250
not shown is also available.
DDU8C3
Doc #00115
DATA DELAY DEVICES, INC.
2
5/19/00
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU8C3 tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values at
low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device
testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU8C3 relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VDD to GND,
located as close as possible to the VDD pin, is
recommended. A wide VDD trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DC Supply Voltage
V
DD
-0.3
7.0
V
Input Pin Voltage
V
IN
-0.3
V
DD
+0.3
V
Storage Temperature
T
STRG
-55
150
C
Lead Temperature
T
LEAD
300
C
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.00V to 3.60V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
High Level Output Voltage
V
OH
3.00
3.20
V
V
DD
= 3.3, I
OH
= MAX
V
IH
= MIN, V
IL
= MAX
Low Level Output Voltage
V
OL
0.10
0.30
V
V
DD
= 3.3, I
OL
= MAX
V
IH
= MIN, V
IL
= MAX
High Level Output Current
I
OH
-24.0
mA
Low Level Output Current
I
OL
24.0
mA
High Level Input Voltage
V
IH
2.50
V
Low Level Input Voltage
V
IL
0.80
V
Input Current
I
IH
0.10
A
V
DD
= 3.3
DDU8C3
Doc #00115
DATA DELAY DEVICES, INC.
3
5/19/00
3 Mt. Prospect Ave. Clifton, NJ 07013
PACKAGE DIMENSIONS
.500 MAX.
1
2
3
4
5
6
7
8
.290
MAX.
.015 TYP.
.070 MAX.
.018
TYP.
.300
.010
3 Equal spaces
each .100
.010
Non-Accumulative
.280
MAX.
.350
MAX.
.010
.002
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
DDU8C3-xx (DIP)
.520 MAX.
1
2
3
4
5
6
7
8
.430
TYP.
.020
TYP.
.040
TYP.
.100
.110
.300
.300
MAX.
.270
TYP.
.010 TYP.
.050
TYP.
DDU8C3-xxA1 (Gull-Wing)
DDU8C3
Doc #00115
DATA DELAY DEVICES, INC.
4
5/19/00
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25
o
C
3
o
C
Load:
1 CMOS Gate
Supply Voltage (VDD): 3.3V
0.1V
C
load
:
5pf
10%
Input Pulse:
High = 3.3V
0.1V
Threshold: 1.65V (Rising & Falling)
Low = 0.0V
0.1V
Source Impedance:
50
Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.5V and 2.8V )
Pulse Width:
PW
IN
= 1.5 x Total Delay
Period:
PER
IN
= 10 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
T1
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
T2
T3
T4
T5
0.5V
0.5V
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
1.5V
1.5V
2.8V
2.8V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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