PDU1032H
5-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1032H)
FEATURES PACKAGES
Digitally programmable in 32 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced &
buffered
Fits 32-pin DIP socket
FUNCTIONAL DESCRIPTION
The PDU1032H-series device is a 5-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pin (OUT) depends
on the address code (A4-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced
into a LOW state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
32
31
26
25
24
17
1
2
7
8
9
11
15
16
GND
ENB
A0
VEE
GND
IN
A3
VEE
GND
OUT
A1
A2
GND
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
OUT
GND
ENB
NC
NC
NC
GND
ENB
NC
NC
NC
NC
NC
NC
NC
GND
ENB
IN
NC
NC
A2
A1
VEE
A0
NC
NC
A4
VEE
A3
NC
NC
NC
NC
NC
NC
NC
VEE
NC
PDU1032H-xxC5 SMD
PDU1032H-xxMC5 Mil SMD
PDU1032H-xx DIP
PDU1032H-xxM Mil DIP
PIN DESCRIPTIONS
IN Signal
Input
OUT Signal
Output
A0-A4 Address Bits
ENB Output
Enable
VEE -5
Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
Total
Delay (ns)
PDU1032H-.5
0.5
0.3
15.5
2.0
PDU1032H-1
1.0
0.5
31
2.0
PDU1032H-2
2.0
0.5
62
3.1
PDU1032H-3
3.0
1.0
93
4.6
PDU1032H-4
4.0
1.0
124
6.2
PDU1032H-5
5.0
1.0
155
7.8
PDU1032H-6
6.0
1.0
186
9.3
PDU1032H-8
8.0
1.0
248
12.4
PDU1032H-10
10.0
1.5
310
15.5
PDU1032H-12
12.0
1.5
372
18.6
PDU1032H-15
15.0
1.5
465
23.2
PDU1032H-20
20.0
2.0
620
31.0
NOTE: Any dash number between .5 and 20
not shown is also available.
Total programmed delay tolerance: 5% or 2ns,
whichever is greater
Inherent delay (TD
0
): 5.5ns typical for dash numbers
up to 5, greater for larger #'s
Setup time and propagation delay:
Address to input setup (T
AIS
): 3.6ns
Disable to output delay (T
DISO
): 1.7ns typical
Operating temperature: 0 to 70 C
Temperature coefficient: 100PPM/C (excludes TD
0
)
Supply voltage V
EE
: -5VDC
5%
Power Dissipation: 615mw typical (no load)
Minimum pulse width: 20% of total delay
2003 Data Delay Devices
Doc #97045
DATA DELAY DEVICES, INC.
1
2/25/03
3 Mt. Prospect Ave. Clifton, NJ 07013
PDU1032H
APPLICATION NOTES
ADDRESS UPDATE
The PDU1032H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, T
OAX
,
is required before the address lines can change.
This time is given by the following relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to "clear" itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
T
DISO
T
OAX
T
AENS
T
ENIS
PW
IN
TD
A
PW
OUT
T
DISH
A4-A0
ENB
IN
OUT
Figure 1: Timing Diagram
A
i-1
A
i
T
AIS
Doc #97045
DATA DELAY DEVICES, INC.
2
2/25/03
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU1032H
Doc #97045
DATA DELAY DEVICES, INC.
3
2/25/03
3 Mt. Prospect Ave. Clifton, NJ 07013
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL
MIN
TYP
UNITS
Total Programmable Delay
TD
T
31
T
INC
Inherent Delay
TD
0
5.5
ns*
Disable to Output Low Delay
T
DISO
1.7
ns
Address to Enable Setup Time
T
AENS
1.0 ns
Address to Input Setup Time
T
AIS
3.6 ns
Enable to Input Setup Time
T
ENIS
3.6 ns
Output to Address Change
T
OAX
See
Text
Disable Hold Time
T
DISH
See
Text
Absolute
PER
IN
16
% of TD
T
Input Period
Suggested
PER
IN
40
% of TD
T
Recommended
PER
IN
200
% of TD
T
Absolute
PW
IN
8
% of TD
T
Input Pulse Width
Suggested
PW
IN
20
% of TD
T
Recommended
PW
IN
100
% of TD
T
* Greater for dash numbers larger than 5
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL
MIN MAX
UNITS
NOTES
DC Supply Voltage
V
EE
-7.0 0.3 V
Input Pin Voltage
V
IN
V
EE
- 0.3
0.3
V
Storage Temperature
T
STRG
-55 150 C
Lead Temperature
T
LEAD
300
C
10
sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS NOTES
High Level Output Voltage
V
OH
-1.020 -0.735 V V
IH
= MAX,50
to -2V
Low Level Output Voltage
V
OL
-1.950 -1.600 V V
IL
= MIN, 50
to -2V
High Level Input Voltage
V
IH
-1.070
V
Low Level Input Voltage
V
IL
-1.480
V
High Level Input Current
I
IH
475
A
V
IH
= MAX
Low Level Input Current
I
IL
0.5
A
V
IL
= MIN
PDU1032H
Doc #97045
DATA DELAY DEVICES, INC.
4
2/25/03
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PACKAGE DIMENSIONS
PDU1032H-xx (Commercial DIP)
PDU1032H-xxM (Military DIP)
.150
.030
1.650 TYP.
1 2
7
8
16
15
11
9
.320
MAX.
.018
TYP.
.400
TYP.
.300
TYP.
.012 TYP.
.020
TYP.
31
32
25
26
24
.100
.600
.700
.800
1.000
1.400
1.500
.075
17
PDU1032H-xxC5 (Commercial SMD)
PDU1032H-xxMC5 (Military SMD)
2.080
.020
.882
.00
.020 TYP.
.040 TYP.
.100
.090
1.100
.280
MAX.
.590
MAX.
.010
.002
.050
.01
.710
.00
.007
.00
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PDU1032H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25
o
C
3
o
C
Load: 50
to -2V
Supply Voltage (Vcc): -5.0V
0.1V
C
load
: 5pf
10%
Input Pulse:
Standard 10KH ECL
Threshold: (V
OH
+ V
OL
) / 2
levels
(Rising & Falling)
Source Impedance: 50
Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width: PW
IN
= 1.5 x Total Delay
Period: PER
IN
= 10 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
ADDRESS SELECT
Timing Diagram For Testing
D
RISE
D
FALL
PER
IN
PW
IN
T
RISE
T
FALL
20%
20%
50%
50%
80%
80%
50%
50%
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #97045
DATA DELAY DEVICES, INC.
5
2/25/03
3 Mt. Prospect Ave. Clifton, NJ 07013
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