DATEL, Inc., Mansfield, MA 02048 (USA.)

Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356

Email: sales@datel.com

Internet: www.datel.com

ADC-321

8-Bit, 50MHz

Video A/D Converter

BIT 8 (LSB)

NO CONNECTION

BIT 7

DIGITAL GROUND (DGND)

BIT 6

OUTPUT ENABLE (OE)

BIT 5

CLAMP ENABLE (CLE)

BIT 4

DIGITAL GROUND (DGND)

BIT 3

CLAMP CONTROL (COP)

BIT 2

CLAMP REF. (V

REF

)

BIT 1 (MSB)

REF. BOTTOM SENSE (V

RBS

)

TEST

REF. BOTTOM (V

)

+DV

(Digital)

ANALOG GROUND (AGND)

TEST

ANALOG GROUND (AGND)

A/D CLOCK

ANALOG IN (V

)

NO CONNECTION

+AV

(Analog)

NO CONNECTION

+AV

(Analog)

CLAMP IN (CLP)

REF. TOP (V

)

+AV

(Analog)

REF. TOP SENSE (V

RTS

)

FEATURES

Low power dissipation (180mW max.)

Input signal bandwith (100MHz)

Optional synchronized clamp function

Low input capacitance (15pF typ.)

+5V or +5V/+3.3V power supply operation

Differential nonlinearity (±½LSB max.)

Optional self-biased reference

CMOS/TTL compatible inputs

Outputs 3-state TTL compatible

Surface mount package

GENERAL DESCRIPTION

The ADC-321 is an 8-bit, high speed, monolithic CMOS, sub-
ranging A/D converter. The ADC-321 achieves a sampling rate
comparable to flash converters by employing a sub-ranging
technique which uses multiple comparator blocks each
containing a sample-and-hold amplifier. The ADC-321 can
operate with either a single +5V or dual +5V and +3.3V power
source to allow easy interfacing with 3.3V logic.

An optional synchronous clamp function useful for video signal
processing is provided. The ADC-321 is well suited for the
portable video signal processors due to its low 125mW typical
power dissipation. The ADC-321 also features ±0.5 LSB max.
differential non-linearity, a self bias function that can eliminate the
need for external references, SNR with THD of 45dB, a small
32-pin QFP package and an operating temperature range
of 40 to +85°C

INPUT/OUTPUT CONNECTIONS

Figure 1. ADC-321 Functional Block Diagram

PIN

FUNCTION

PIN

FUNCTION

1 BIT 8 (LSB)

2 BIT 7

3 BIT 6

4 BIT 5

Reference

Supply

4-Bit

Lower

Sampling

Comparator

Clock

Generator

4-Bit

Upper

Sampling

Comparator

4-Bit

Lower

Encoder

4-Bit

Upper

Encoder

Upper

Data

Latch

Lower

Data

Latch

D-FF

31 DGND

30 OUTPUT ENABLE

5 BIT 4

6 BIT 3

7 BIT 2

8 BIT 1 (MSB)

12 A/D CLOCK

15 CLAMP IN

9 TEST (Open)

10 +DV

11 TEST (Open)

+AV

RTS

AGND

RBS

REF

CLAMP CONTROL

CLAMP ENABLE

DGND

ADC-321

DIGITAL OUTPUTS

(continued)

MIN.

TYP.

MAX.

UNITS

Output Data Delay
(OE = 0V, C

= 15pF)

(@ +DV

= +5V)

PLH

5.5

9.5

12.0

PHL

5.5

8.5

12.0

(@+DV

= +3.3V)

PLH

4.3

11.8

16.3

PHL

4.3

7.6

16.3

3-State Output Enable Time
(R

= 1k

, C

= 15pF)

(@ +DV

= +5V)

PZH

2.5

4.5

8.0

PZL

2.5

6.0

8.0

(@+DV

= +3.3V)

PZH

3.0

7.0

9.0

PZL

3.0

5.0

9.0

3-State Output Disable Time
(R

= 1k

, C

= 15pF)

(@+DV

= +5V)

PHZ,

PLZ

3.5

5.5

7.5

(@+DV

= +3.3V)

PHZ,

PLZ

2.5

5.5

8.0

CLAM CIRCUIT

Clamp Offset Voltage

Clamp Pulse Width

1.75

2.75

3.75

µA

PERFORMANCE

Resolution

Bit

Sampling Rate, maximum, F

MHz

minimum, F

0.5

MHz

Aperature Delay (Tds)

Integral Linearity Error

±0.7

±1.5

LSB

Diff. Linearity Error

±0.3

±0.5

LSB

Diff. Gain Error

Diff. Phase Error

1.5

deg

S/N Ratio with THD

= 100kHz)

= 500kHz)

= 1MHz)

= 3MHz)

= 10MHz)

= 25MHz)

Spurious Free Dynamic Range

= 100kHz)

= 500kHz)

= 1MHz)

= 3MHz)

= 10MHz)

= 25MHz)

POWER REQUIREMENTS

Power Supply

+AV

+4.75

+5.0

+5.25

Volts

+DV

+3.0

+5.5

Volts

|AGND DGND|

100

Power Supply Current
1. AI

(@ +DV

= +5V)

2. AI

(@ +DV

= +3.3V)

Power Dissipation

125

180

ENVIRONMENTAL/PHYSICAL

Operating Temp. Range, Case

+85

°C

Storage Temperature Range

+150

°C

Package Type

32-pin, plastic QFP

Weight

0.007 ounces (0.2 grams)

ANALOG INPUTS

MIN.

TYP.

MAX.

UNITS

Input Voltage Range

+0.5

+2.5

Volts

Input Capacitance

(@ V

= +1.5Vdc +0.07V

RMS)

Input Signal Bandwidth

1dB (@ R

= 33

)

MHz

3dB (@ R

= 33

)

100

MHz

REFERENCE INPUTS

Reference Resistance

260

370

480

Reference Current

4.1

5.4

7.7

Reference Voltage

+2.7

Volts

1.7

Volts

Self Bias Voltage

+0.52

+0.56

+0.60

Volts

1.80

1.92

2.04

Volts

Capacitance (V

, V

RTS

, V

RBS

)

Offset Voltage

DIGITAL INPUTS

Logic Levels

Input Voltage "1"

2.2

Volts

Input Voltage "0"

+0.8

Volts

Input Current

A/D CLK

240

µA

CLP, CLE

240

µA

240

µA

Input Capacitance

A/D Clock Pulse Width

(tpw1)

(tpw0)

DIGITAL OUTPUTS

MIN.

TYP.

MAX.

UNITS

Output Current (OE = 0V)

(@ +DV

= +5V)

"1"

"0"

Output Current (OE = 0V)

(@ +DV

= +3.3V)

"1"

1.2

"0"

2.4

Output Current

(@ OE = +3V)

"1"

"0"

Capacitance

PARAMETERS

LIMITS

UNITS

Power Supply Voltage (+AV

, +DV

)

0.5 to 7

Volts

Analog Input Voltage, (V

)

0.5 to +AV

+ 0.5

Volts

Reference Input Voltage (V

, V

)

0.5 to +AV

+ 0.5

Volts

Digital Input Voltage (V

, V

)

0.5 to +AV

+ 0.5

Volts

Digital Output Voltage (V

, V

)

0.5 to +DV

+ 0.5

Volts

ABSOLUTE MAXIMUM RATINGS

FUNCTIONAL SPECIFICATIONS

Typical at T

= 25°C, V

= +2.5V, V

= +0.5V, +AV

= +5V, +DV

= +3V to +5.5V,

= 50MHz unless otherwise specified.

= +25°C)

Footnotes:

See technical note 6

Pin 25 tied to AGND and pin 17 tied to +AV

+AV

= +4.75 to +5.25V and +DV

= 3 to +5.5V, full operating tem. range.

= 0V and V

= +AV

, full operating temp. range

= +DV

0.8V and V

= +0.4V, full operating temp. range

+DVS = +3 to +5.5V, full operating temp. range

OE: +3 to 0V change

OE: 0 to +3V change

2.75µs clamp pulse width, 14.3MHz sampling,
15.75kHz clamping rate

The clamp pulse width given is for NTSC. For other processing
systems adjust the rate to the clamp pulse cycle (1/15.75kHz for
NTSC) to equal the value for NTSC.

NTSC 40IRE ramp, 14.3MHz sampling

50MHz sampling, +AV

= +5V

ADC-321

TECHNICAL NOTES

1. The ADC-321 is a monolithic CMOS device. It should be

handled carefully to prevent static charge pickup.

2. It has separate power supply terminals +AV

(pins 16, 19

and 20) and +DV

(pin 10) for the internal analog and digital

circuits. It is recommended that both +AV

and +DV

powered from a single source

Other external digital circuits must be powered with a
separate +DV

. A time lag between the two power supplies

could induce latch up when power is turned on if separate
supplies are used. The operating range of +DV

is from

+3.0V to +5.5V and it allows the use of a common power
supply with 3.3V digital systems. The +3.3V power for +DV

in this case should be taken or derived from the +AV

supply

to avoid latch up. No power supply terminal should be left
open.

3. The ADC-321 has separate grounds, the analog GND (pins

22 and 23) and digital GND (pins 28 and 31). Separate and
substantial AGND and DGND ground planes are required.
These grounds have to be connected to one earth point
underneath the device. Digital returns should not flow through
analog grounds. Connect all ground lines to the power point.

4. Bypass all power lines to GND with 0.1µF ceramic chip

capacitors as close to the device as possible. This is
very important.

5. Even though the analog input capacitance is a low 15pF, it is

recommended that high frequency input be provided via a
high-speed buffer amplifier. A parasitic oscillation may be
generated when a high-speed amplifier is used. A 33 ohm
resistor inserted between the output of an amplifier and the
analog input of the ADC-321 will improve the situation. Kick
back noise from A/D CLOCK pulses will be observed at the
analog input terminal, but this has no influence on the ADC-
321 performance.

6. Apply +2.5V to V

(pin 18, reference top) and 0.5V to V

(pin 24 reference bottom) to obtain an analog input range of
+0.5V to +2.5V. Conversion accuracy is dependent on stable
reference voltages. Provide reference inputs via amplifiers
that have enough driving power to avoid noise problems.
Keep to the following equations;

+2.7V, | V

1.7V

The ADC-321 has a self bias function which allows the
device to work without external references. Connect V

RTS

(pin 17, self bias top) to +AV

and V

RBS

(pin 25, self bias

bottom) to the analog GND to obtain an analog input range of
+0.56 to +2.48V. Typical voltages at V

(pin 18) and V

(pin

24) will then be +2.48V and +0.56V respectively. Under an
application where this self bias function is used, the effects of
temperature changes are minimal. Voltage changes of the
+5V supply have direct influence on the performance of the
device. The use of external references is recommended for
applications sensitive to gain error, no ac signals can be
used as references for this device.

7. A voltage up to +AV

+ 0.5V can be applied to each digital

input even when +3.3V is powered to +DV

, but the digital

output voltage never exceeds +DV

8. Layout A/D CLOCK pulse input (pin 12) as short as possible

for minimum influence on other signals. Use of a 100 ohm
series resistor is recommended to protect the device as
there may be some voltage difference and turn-on-time lag
on the power supplies. Analog inputs signals are sampled at
the falling edge of an A/D CLOCK pulse and digital data
become available at the rising edge of an A/D CLOCK pulse
that is delayed by 2.5 clock cycles. The A/D CLOCK are
positive pulse that have 50% duty cycle. The minimum clock
pulse width is 10 nsec for both high and low levels. Keep it
low level while A/D conversions
are on hold.

9. Digital output is 3-state. To enable 3-state outputs connect

the OUTPUT ENABLE (pin 30) to GND. To disable, connect
it to +DV

. The output is recommended to be latched and

buffered through output registers. The device may be
damaged if a voltage higher than +DV

+ 0.5V is given to

digital output pins while at high impedance level.

10. The 50MHz sampling rate is guaranteed. It is not recom-

mended to use this device at sampling rates slower than
500kHz because the droop characteristics of the internal
sample and hold exceed the limit required to maintain the
specified accuracy of the device. Also, burst mode sampling
is not recommended.

11. The ADC-321 has a clamp function. This clamp is enabled

when CLAMP ENABLE (pin 29) is tied to GND and is
disabled when tied to +DV

or left open. Clamp pulse inputs

(pin 15) are effective when this clamp function is enabled and
signals are clamped whole, this clamp pulse is low. The
clamp reference input (pin 26) is set by an external trim. The
CCP terminal (pin 27) integrates the clamp control voltage
across an external capacitor. Refer to Figure 4 for examples
of various ways to use this clamp function.

12. The TEST 1 and 2 (pins 9 and 11) are not used. Always

leave them open.

ADC-321

Figure 2-1. ADC-321 Timing Diagram

Figure 2-2. ADC-321 Timing Diagram

MSB

LSB

Table 2: Digital Output Coding

OUTPUT CODE

0 0

+7.812mV

0 0

+0.9922V

0 1

+1.000V

1 0

+1.500V

1 1

+1.9922V

1 1

THEORY OF OPERATION

(See Functional Block Diagram, Figure 1, and Timing
Diagrams, Figure 2)

1. The DATEL ADC-321 is a 2-step parallel A/D converter

featuring a 4-bit upper comparator group and two 4-bit
lower comparator groups, each with built-in sample and
hold. A reference voltage equal to the voltage between
(V

)/16 is constantly applied to the 4-bit upper

comparator block. A voltage corresponding to the upper
data is fed through the reference supply to the lower data.
V

RTS

and V

RBS

pins provde the self generation function for

(reference voltage top) and V

(reference voltage

bottom) voltages.

2. This converter uses an offset cancelation type comparator

and operates synchronously with the external clock. It
features various operating modes which are shown in the
Timing Diagram (Figure 2) by the symbols S, H and C.
These characters stand for Input Sampling (Auto Zero)
Mode, Input Hold Mode and Comparison Mode.

3. The operation of the respective parts is as indicated in

Figure 2-3. For instance, input voltage N is sampled with
the falling edge of the first clock by means of the upper

comparator block and the lower comparator A block. Input
voltage N+1 is sampled with the falling edge of the second
clock by means of the upper comparator block and lower
comparator B block. The upper comparator block finalizes
comparison data UD(N) with the rising edge of the second
clock. The lower comparator block finalizes comparison
data LD(N) with the rising edge of the third clock. UD(N)
and LD(N) are combined and routed to the output as Output
Data N with the rising edge of the fourth clock. Thus there
is a 2.5 clock delay from the analog input sampling point to
the digital data output.

1.3V

tr = 4.5ns

90%

10%

phz

plz

90%

tr = 4.5ns

10%

pzh

1.3V

pzl

/(=DGND)

OE INPUT

OUTPUT 1

OUTPUT 2

CLOCK 1.3V

tr = 4ns

tf = 4ns

90%

10%

DATA

OUTPUTS

0. 3 DV

0. 7 DV

pLH

pHL

ADC-321

Figure 2-3. ADC-321 Timing Diagram

A/D CLOCK

+5V (A)

+5V (D)

47µF

10µH

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8 (LSB)

10µH

+12V

12V

0.1µF

10pF

0.1µF

500

10µF

500

100

+5V (A)

+12V

500

470µF

180

47µF

ANALOG IN

120

12V

500

ADC-321

0.1µF

74HC04

0.1µF

Figure 3. Typical Connection Diagram

CLOCK 1.3V

ANALOG

SIGNAL

DATA

OUTPUTS

N+1

N+2

N+3

PW1

PW0

PLH

PHL

Internal Operation of the ADC-321

S = Sample Mode, H = Hold Mode, C = Comparate Mode

LOWER OUTPUT

DATA 2

LD (N3)

LD (N1)

LD (N+1)

LOWER SAMPLING

COMPARTOR 2

H (N1)

C (N1)

S (N+1)

H (N+1)

C (N+1)

S (N+3)

H (N+3)

LOWER OUTPUT

DATA 1

LD (N2)

LD (N)

S (N)

S (N+1)

C (N)

C (N+1)

UPPER SAMPLING

COMPARTOR

S (N+2)

C (N+2)

S (N+3)

C (N+3)

UPPER OUTPUT

DATA

UD (N1)

UD (N)

UD (N+1)

UD (N+2)

LOWER SAMPLING

COMPARTOR 1

S (N)

H (N)

C (N)

S (N+2)

H (N+2)

C (N+2)

10ns min. 10ns min.

0ns typ.

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